EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 9
![EVAL DEV QUICK START ADUC7032](/photos/9/24/92482/eval-aduc7032qspz_sml.jpg)
EVAL-ADUC7032QSPZ
Manufacturer Part Number
EVAL-ADUC7032QSPZ
Description
EVAL DEV QUICK START ADUC7032
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of EVAL-ADUC7032QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
For Use With/related Products
ADuC7032
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 9 of 116
- Download datasheet (3Mb)
Table 3. SPI Master Mode Timing (PHASE Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data output setup time before SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SCLK
SCLK
MOSI
MISO
t
DOSU
t
DSU
1
1
MSB IN
MSB
t
DHD
t
SH
Figure 3. SPI Master Mode Timing (PHASE Mode = 0)
t
DF
2
HCLK
t
DAV
2
= t
UCLK
t
SL
/2
Rev.0 | Page 9 of 116
CD
t
DR
.
BITS[6:1]
BITS[6:1]
Min
0
3 × t
UCLK
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
½ t
3.5
3.5
3.5
3.5
LSB IN
SL
t
SR
LSB
HCLK
HCLK
t
SF
Max
(2 × t
UCLK
) + (2 × t
ADuC7032-8L
HCLK
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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