EVAL-ADUC7032QSPZ Analog Devices Inc, EVAL-ADUC7032QSPZ Datasheet - Page 89
![EVAL DEV QUICK START ADUC7032](/photos/9/24/92482/eval-aduc7032qspz_sml.jpg)
EVAL-ADUC7032QSPZ
Manufacturer Part Number
EVAL-ADUC7032QSPZ
Description
EVAL DEV QUICK START ADUC7032
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of EVAL-ADUC7032QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
For Use With/related Products
ADuC7032
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 89 of 116
- Download datasheet (3Mb)
High Voltage Configuration 0 Register
Name: HVCFG0
Address: Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the function of high voltage circuits on the ADuC7032-8L. This register is not an MMR and does
not appear in the MMR memory map. It is accessed via the HVCON registered interface. Data to be written to this register is loaded via
the HVDAT MMR and data is read back from this register via the HVDAT MMR.
Table 74. HVCFG0 Bit Designations
Bit
7
6
5
4
3
2
1 to 0
Description
WU Thermal Shutdown Disable.
Precision Oscillator Enable Bit.
Reserved. This bit is reserved and should be written as 0 by user code.
WU Assert Bit.
PSM Enable Bit.
Low Voltage Flag Enable Bit.
LIN Operating Mode.
These bits enable/disable the LIN driver.
1 = disable the automatic shutdown of the WU driver when a thermal event occurs.
0 = enable the automatic shutdown of the WU driver when a thermal event occurs.
1 = enable the precision 131 kHz oscillator. The oscillator start-up time is typically 70 μs (including high voltage interface latency
of 10 μs).
0 = power-down the precision 131 kHz oscillator.
1 = assert the external WU pin high.
0 = pull the external WU pin low via an internal 10 kΩ pull-down resistor.
0 = disable the power supply (voltage at the VDD pin) monitor.
1 = enable the power supply (voltage at the VDD pin) monitor. When IRQ3 (IRQEN[16]) is enabled, the PSM generates an
interrupt if the voltage at the VDD pin drops below 6.0 V.
0 = disable the low voltage flag function.
1 = enable the low voltage flag function. The low voltage flag can be interrogated via HVMON[3] after power-up to determine if
the REG_DVDD voltage previously dropped below 2.1 V.
00 = LIN disabled.
01 = reserved (not LIN 2.0 compliant).
10 = LIN enabled.
11 = reserved.
Rev.0 | Page 89 of 116
ADuC7032-8L
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