MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 418

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

13.4 QADC64 Bus Interface
13.5 Module Configuration
13.5.1 Low-Power Stop Mode
13.5.2 Freeze Mode
MPC555
USER’S MANUAL
The QADC64 supports to 8-bit, 16-bit, and 32-bit data transfers, at even and odd ad-
dresses. Coherency of results read, (ensuring that all results read were taken consec-
utively in one scan) is not guaranteed. For example, if two consecutive 16-bit locations
in a result area are read, the QADC64 could change one 16-bit location in the result
area between the bus cycles. There is no holding register for the second 16-bit loca-
tion. All read and write accesses that require more than one 16-bit access to complete
occur as two or more independent bus cycles. Depending on bus master protocol,
these accesses could include misaligned and 32-bit accesses.
Normal reads-from and writes-to the QADC64 require two clock cycles. However, if the
CPU tries to access locations that are also accessible to the QADC64 while the
QADC64 is accessing them, the bus cycle will require additional clock cycles. The
QADC64 may insert from one to four wait states in the process of a CPU read from or
write to such a location.
The QADC64 module configuration register (QADC64MCR) defines freeze and stop
mode operation, supervisor space access, and interrupt arbitration priority. Unimple-
mented bits read zero and writes have no effect. QADC64MCR is typically written once
when software initializes the QADC64, and not changed thereafter. Refer to
QADC64 Module Configuration Register
When the STOP bit in QADC64MCR is set, the clock signal to the A/D converter is dis-
abled, effectively turning off the analog circuitry. This results in a static, low power con-
sumption, idle condition. Low-power stop mode aborts any conversion sequence in
progress. Because the bias currents to the analog circuits are turned off in low-power
stop mode, the QADC64 requires some recovery time to stabilize the analog circuits
after the STOP bit is cleared.
In low-power stop mode, the BIU state machine and logic do not shut down, and the
QADC64MCR, the interrupt register (QADC64INT), and the test register
(QADC64TEST) are fully accessible and are not reset. The data direction register
(DDRQA), port data register (PORTQA/PORTQB), and control register zero (QACR0)
are not reset and are read-only accessible. The RAM is not reset and is not accessible.
Control register one (QACR1), control register two (QACR2), and the status registers
(QASR0 and QASR1) are reset and are read-only accessible. In addition, the periodic/
interval timer is held in reset during stop mode.
If the STOP bit is clear, low-power stop mode is disabled. The STOP bit must be clear
to program CCWs into RAM or read results from RAM.
The QADC64 enters freeze mode when background debug mode is enabled and a
breakpoint is processed. This is indicated by assertion of the FREEZE line on the
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Rev. 15 October 2000
for register and bit descriptions.
MOTOROLA
13.12.1
13-6