MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 719

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MPC555
USER’S MANUAL
DSCK
The development port provides a full duplex serial interface for communications be-
tween the internal development support logic of the CPU and an external development
tool. The development port can operate in two working modes: the trap enable mode
and the debug mode.
The trap enable mode is used in order to shift into the CPU internal development sup-
port logic the following control signals:
Figure 21-5 Functional Diagram of MPC555 / MPC556 Debug Mode Support
DSDI
1. Instruction trap enable bits, used for on the fly programming of the instruction
2. Load/store trap enable bits, used for on the fly programming of the load/store
3. Non-maskable breakpoint, used to assert the non-maskable external break-
4. Maskable breakpoint, used to assert the maskable external breakpoint
5. VSYNC, used to assert and negate VSYNC
/
MPC556
breakpoint
breakpoint
point
BKPT, TE,
VSYNC
CPU Core
ECR
DER
9
DEVELOPMENT SUPPORT
Rev. 15 October 2000
TECR
Development Port
Development Port
Control Logic
Shift Register
32
35
DPDR
DPIR
32
Internal
Bus
Development
Port
SIU/
EBI
Logic
Support
MOTOROLA
EXT
BUS
VFLS,
DSDO
FRZ
21-23

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