MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 96

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.5.2 Three-Volt Output Pad
2.5.2.1 Type A Interface
MPC555
USER’S MANUAL
These interface signals are referred to in the following pad descriptions and shown in
the pad diagrams.
The output driver of a 3-V output-only pad can be configured to drive a 25-pF or 50-pF
load. There are two subtypes: one with a pull-up device and the other with a pull-down
device. The SPRDS and OE signals enable the pull-up and pull-down resistors.
This pad has a pull-up device to 3 V which can be conditionally turned off based on the
value placed on OE. For a totem pole (push pull) pin with no three-state drive time, the
OE can be connected to VDD, indicating a continuous drive. For a continuous drive,
the pull-up can be disabled.
• Drive select – Selects the drive strength of the pad. For example, data pin drivers
• Synchronizer clock – Some pins have synchronizer logic to handle metastable
• Slew rate control – GPIO pins have slow slew rates, with edge rates in the range
• Hysteresis input – Slow pads contains hysteresis input buffers to reduce the sen-
• Open drain enable – For selected 3-V / 5-V pads, this signal determines the type
• Pull resistor disable select (PRDS) – Reflects the state of the PRDS bit in the pad
• Special pull resistor disable select (SPRDS) – Reflects the state of the SPRDS
• Analog – Analog input signals to the QADC. The corresponding digital interface
• JTAG – Joint Test Access Group related signals that are used for connectivity
/
can be configured to drive a 25-pF load or a 50-pF load.
signals at the input of a pin. For pads that have synchronizers and support syn-
chronized or normal data input, the corresponding interface signals to the internal
logic are “Normal Data In” and “Sync Data In.”
of 90 ns to 600 ns. The slew rate and weak pull-up/pull-down characteristics of
these pins are controlled by bits in the PDMCR, see
ration Register
controllable slew rates, see
sitivity to noises. The input hyst_sel is used to configure the pad to provide hys-
teresis according to the pad configuration.
of drive (open drain or totem pole) seen at the pin.
module configuration register (PDMCR). This signal controls the pull-up/pull-
down resistor for the SGPIO pins and the pins for the modules on the UIMB.
bit in the PDMCR. For pins that support bus arbitration functionality multiplexed
with opcode-tracking and debug functionality, this signal controls the pull-up re-
sistors.
signals are referred to as “Dig. In” and Dig. Out”.
tests at the board level. These signals are not shown in the pad block diagrams
in this section. In addition, the effect of the pull-up/pull-down resistors is not illus-
trated in the pad block diagrams.
MPC556
(PDMCR). For a description of PDMCR bits SLRC[0:3] that have
SIGNAL DESCRIPTIONS
Rev. 15 October 2000
Table
2-3.
2.4.2 Pad Module Configu-
MOTOROLA
2-38