MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 697

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.1 Overview
21.2 Program Flow Tracking
MPC555 / MPC556
USER’S MANUAL
The visibility and controllability requirements of emulators and bus analyzers are in op-
position to the trend of modern microcomputers and microprocessors where many bus
cycles are directed to internal resources and are not visible externally.
In order to enhance the development tool visibility and controllability, some of the de-
velopment support functions are implemented in silicon. These functions include pro-
gram flow tracking, internal watchpoint, breakpoint generation, and emulation while in
debug mode.
This section covers program flow tracking support, breakpoint/watchpoint support, de-
velopment system interface support (debug mode) and software monitor debugger
support. These features allow the user to efficiently debug systems based on the
MPC555 / MPC556.
The mechanism described below allows tracking of program instruction flow with al-
most no performance degradation. The information provided may be compressed and
captured externally and then parsed by a post-processing program using the microar-
chitecture defined below.
The program instructions flow is visible on the external bus when the MPC555 /
MPC556 is programmed to operate in serial mode and show all fetch cycles on the ex-
ternal bus. This mode is selected by programming the ISCT_SER (instruction fetch
show cycle control) field in the I-bus support control register (ICTRL), as shown in
ble
appear on the external bus. Processor performance is, therefore, much lower than
when working in regular mode.
These features, together with the fact that most fetch cycles are performed internally
(e.g., from the I-cache), increase performance but make it very difficult to provide the
user with the real program trace.
In order to reconstruct a program trace, the program code and the following additional
information from the MCU are needed:
• A description of the last fetched instruction (stall, sequential, branch not taken,
• The addresses of the targets of all indirect flow change. Indirect flow changes in-
21-21. In this mode, the processor is fetch serialized, and all internal fetch cycles
branch direct taken, branch indirect taken, exception taken)
clude all branches using the link and count registers as the target address, all ex-
ceptions, and rfi, mtmsr and mtspr (to some registers) because they may cause
a context switch.
DEVELOPMENT SUPPORT
DEVELOPMENT SUPPORT
Rev. 15 October 2000
SECTION 21
MOTOROLA
21-1
Ta-