MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 477

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.7.1 QSPI Registers
MPC555
USER’S MANUAL
A dedicated 160-byte RAM is used to store received data, data to be transmitted, and
a queue of commands. The CPU can access these locations directly. This allows serial
peripherals to be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 32 serial transfers without CPU
intervention. Each queue entry contains all the information needed by the QSPI to in-
dependently complete one serial transfer.
A pointer identifies the queue location containing the data and command for the next
serial transfer. Normally, the pointer address is incremented after each serial transfer,
but the CPU can change the pointer value at any time. Support for multiple-tasks can
be provided by segmenting the queue.
The QSPI has four peripheral chip-select pins. The chip-select signals simplify inter-
facing by reducing CPU intervention. If the chip-select signals are externally decoded,
16 independent select signals can be generated.
Wrap-around mode allows continuous execution of queued commands. In wrap-
around mode, newly received data replaces previously received data in the receive
RAM. Wrap-around mode can simplify the interface with A/D converters by continu-
ously updating conversion values stored in the RAM.
Continuous transfer mode allows transfer of an uninterrupted bit stream. From 8 to 512
bits can be transferred without CPU intervention. Longer transfers are possible, but
minimal intervention is required to prevent loss of data. A standard delay of 17 IMB
clocks (0.8 µs with a 40-MHz IMB clock) is inserted between the transfer of each
queue entry.
The QSPI memory map, shown in
control registers, four QSPI control registers (SPCR[0:3]), the status register (SPSR),
and the QSPI RAM. Registers and RAM can be read and written by the CPU. The
memory map can be divided into supervisor-only data space and assignable data
space. The address offsets shown are from the base address of the QSMCM module.
Refer to
internal memory map.
/
MPC556
1.3 MPC555 / MPC556 Address Map
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
Table
14-12, includes the QSMCM global and pin
for a diagram of the MPC555 / MPC556
MOTOROLA
14-15