IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet
IDT72V3684
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IDT72V3684 Summary of contents
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... FIFO2 Status Flag Logic Read Write Pointer Pointer RAM ARRAY 16,384 32,768 x 36 65,536 x 36 Mail 2 Register 1 TM WITH BUS-MATCHING IDT72V3684 IDT72V3694 IDT72V36104 36 36 FIFO2, Mail2 Reset Logic Port-B Control Logic 4677 drw01 NOVEMBER 2003 MBF1 EFB/ORB AEB FWFT ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 DESCRIPTION The IDT72V3684/72V3694/72V36104 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are mono- lithic, high-speed, low-power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6 ...
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... Initiating any operation (by activating control CC inputs) will immediately take the device out of the power down state. The IDT72V3684/72V3694/72V36104 are characterized for operation from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available. They are fabricated using IDT’s high speed, submicron CMOS technology. ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/O AEA Port A Almost- O Empty Flag AEB Port B Almost- O Empty Flag AFA Port A Almost- O Full Flag AFB Port B Almost- O Full Flag ...
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... FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB. ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I (2) V Output Voltage Range O I Input Clamp Current (V ...
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... BUS-MATCHING 16,384 32,768 and 536 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3684/72V3694/72V36104 with CLKA CC(f) and CLKB set All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected S to normalize the graph to a zero capacitance load ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE ο ο (Vcc = 3.3V 0.15V +70 C; JEDEC JESD8-A compliant) ± Symbol Parameter f Clock Frequency, CLKA or CLKB ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C ο ο (Vcc = 3.3V 0.15V +70 C; JEDEC JESD8-A compliant) ± Symbol Parameter t Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 A Propagation Delay Time, CLKA↑ ...
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... After power up, a Master Reset operation must be performed by providing a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, each of the two FIFO memories of the IDT72V3684/72V3694/72V36104 undergoes a com- plete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions ...
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... The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 16,380 for the IDT72V3684 32,764 for the IDT72V3694; and 1 to 65,532 for the IDT72V36104. After all the offset registers are ...
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... X1, Y2, and finally, X2. The first-bit write stores the most significant bit of the Y1 register and the last-bit write stores the least significant bit of the X2 register. Each register value can be programmed from 1 to 16,380 (IDT72V3684 32,764 (IDT72V3694 65,532 (IDT72V36104). When the option to program the offset registers serially is chosen, the Port A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes) Number of Words in FIFO Memory (3) IDT72V3684 IDT72V3694 (X1+1) to [16,384-(Y1+1)] (X1+1) to [32,768-(Y1+1)] (16,384-Y1) to 16,383 (32,768-Y1) to 32,767 16,384 NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. ...
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... IDT72V3684, IDT72V3694, or IDT72V36104 respec- tively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [16,384-(Y+1)], [32,768-(Y+1)], or [65,536-(Y+1)] for the IDT72V3684, IDT72V3694, or IDT72V36104 respectively. Note that a data word present in the FIFO output register has been read from memory. 14 ...
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... Figure 2. Only 36-bit long word data is written to or read from the two FIFO memories on the IDT72V3684/72V3694/72V36104. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. These bus-matching operations are not available when transferring data via mailbox registers ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 BYTE ORDER ON PORT A: B35 B27 BYTE ORDER ON PORT SIZE SIZE B35 B27 BE BM SIZE B35 B27 BE BM SIZE B35 ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLKA CLKB t RSTS MRS1 BE/FWFT FS2, FS1,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 RTM LOW NOTES: 1. FIFO2 Master Reset (MRS2) is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset, MRS1 must toggle simultaneously with MRS2. ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKA 1 4 MRS1, MRS2 t FSS t FSH FS2 t t FSS FSH FS1,FS0 0,0 FFA/IRA ENA A0-A35 CLKB FFB/IRB NOTES: is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising 1 ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLK t CLKH t CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ENA A35 NOTE: 1. Written to FIFO1. Figure 7. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes) ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKB FFB/IRB HIGH CSB W/RB MBB ENB B0-B17 DATA SIZE TABLE FOR WORD WRITES TO FIFO2 (1) SIZE MODE WRITE BM SIZE NOTE selected at Master Reset; BM and SIZE must be static throughout device operation. ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (Standard Mode B0-B35 (FWFT Mode) NOTE: 1. Read From FIFO1. DATA SIZE TABLE FOR FIFO LONG-WORD READS FROM FIFO1 ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKB EFB/ORB HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode) t MDV B0-B8 (FWFT Mode) NOTE: 1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate for byte-size reads. ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLKA CSA LOW WRA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IRA HIGH A0-A35 W1 t SKEW1 CLKB ORB FIFO1 Empty CSB LOW W/RB HIGH ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKA CSA LOW HIGH WRA t t ENS2 ENH MBA t t ENH ENS2 ENA FFA HIGH A0-A35 W1 t SKEW1 CLKB EFB FIFO1 Empty CSB LOW W/RB HIGH ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH B0-B35 W1 t SKEW1 CLKA ORA FIFO2 Empty CSA LOW W/RA LOW LOW ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENS2 ENH ENB FFB HIGH B0-B35 t SKEW1 CLKA EFA FIFO2 Empty CSA LOW LOW W/RA LOW MBA ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB ORB HIGH B0-B35 Previous Word in FIFO1 Output Register CLKA FIFO1 Full IRA CSA LOW HIGH ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA ORA HIGH A0-A35 Previous Word in FIFO2 Output Register CLKB IRB FIFO2 FULL CSB LOW W/RB LOW ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous Word in FIFO2 Output Register CLKB FFB FIFO2 Full CSB LOW W/RB LOW ...
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... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO Maximum FIFO Depth = 16,384 for the IDT72V3684, 32,768 for the IDT72V3694, 65,536 for the IDT72V36104. ...
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... FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO Maximum FIFO Depth = 16,384 for the IDT72V3684, 32,768 for the IDT72V3694, 65,536 for the IDT72V36104. ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 65, 536 CLKB CSB W/RB MBB ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA t EN A0-A35 FIFO2 Output Register NOTE Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don’t care inputs). In this first case A0-A17 will have valid data (A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don’ ...
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... No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit setup procedure 16,384, 32,768 and 65,536 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively. Figure 29. Retransmit Timing for FIFO1 (IDT Standard Mode) ...
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... W1 = first word written to the FIFO2 after Master Reset on FIFO2 more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRB will be LOW throughout the Retransmit setup procedure 16,385, 32,769 and 65,537 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively. TM ...
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... IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO BUS-MATCHING 16,384 32,768 and 536 PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PZL t PLZ Low-Level Output ...
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ORDERING INFORMATION IDT X XX XXXXXX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 10/31/2000 pgs and 36 12/14/2000 pgs. 4 and 5. 02/08/2001 pgs. 5 ...