74F1071MSAX Fairchild Semiconductor, 74F1071MSAX Datasheet

74F1071MSAX

Manufacturer Part Number

74F1071MSAX

Description

IC UNDER/OVERSHOOT CLAMP 20SSOP

Manufacturer

Fairchild Semiconductor

Type

Fast/Faster Bipolar Logicr

Datasheet

1.74F1071MSAX.pdf (6 pages)

Specifications of 74F1071MSAX

Voltage - Reverse Standoff (typ)

Voltage - Breakdown

Polarization

9 Channel Array - Bidirectional

Mounting Type

Surface Mount

Package / Case

20-SSOP

Output Voltage Range

5.25 V

Input Voltage Range

- 0.5 V to + 6.0 V

Input Current

50 mA

Power Dissipation

800 mW

Operating Temperature Range

0 C to + 70 C

Mounting Style

SMD/SMT

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Power (watts)

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

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74F1071SC

74F1071SCX_NL

(Note 1)

74F1071MSA

74F1071MSAX_NL

(Note 1)

74F1071MTC

74F1071MTCX_NL

(Note 1)

74F1071

18-Bit Undershoot/Overshoot Clamp

and ESD Protection Device

General Description

The 74F1071 is an 18-bit undershoot/overshoot clamp

which is designed to limit bus voltages and also to protect

more sensitive devices from electrical overstress due to

electrostatic discharge (ESD). The inputs of the device

aggressively clamp voltage excursions nominally at 0.5V

below and 7V above ground.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Connection Diagram

Note: Simplified Component Representation

FAST

Order Number

is a registered trademark of Fairchild Semiconductor Corporation.

Package

Number

MSA20

MTC20

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

Pb-Free 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

DS011685

Features

18-bit array structure in 20-pin package

FAST

Dual center pin grounds for min inductance

Robust design for ESD protection

Low input capacitance

Optimum voltage clamping for 5V CMOS/TTL

applications

Package Description

Bipolar voltage clamping action

October 1994

Revised March 2005

www.fairchildsemi.com

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