DSPIC33FJ32GS406-I/PT Microchip Technology, DSPIC33FJ32GS406-I/PT Datasheet - Page 146

• Manufacturer Part Number: DSPIC33FJ32GS406-I/PT
• Description: IC MCU/DSP 32KB FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GS406-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SCI, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Core Frequency: 40MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 32KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 7-17:
DS70591C-page 146
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-12
bit 11
bit 10
bit 9
bit 8-7
bit 6
bit 5-3
bit 2
bit 1
bit 0
Note 1: Interrupts disabled on devices without ECAN™ modules.
U-0
U-0
—
—
Unimplemented: Read as ‘0’
QEI2IE: QEI2 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
PSESMIE: PWM Special Event Secondary Match Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit
1 = Interrupt request occurred
0 = Interrupt request not occurred
Unimplemented: Read as ‘0’
U2EIE: UART2 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
C1TXIE
R/W-0
U-0
—
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
(1)
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
QEI2IE
R/W-0
U-0
—
(1)
R/W-0
U2EIE
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
PSESMIE
U1EIE
R/W-0
R/W-0
U-0
U-0
—
—
bit 8
bit 0