DSPIC33FJ32GS406-I/PT Microchip Technology, DSPIC33FJ32GS406-I/PT Datasheet - Page 234

• Manufacturer Part Number: DSPIC33FJ32GS406-I/PT
• Description: IC MCU/DSP 32KB FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GS406-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SCI, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Core Frequency: 40MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 53
• Flash Memory Size: 32KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-6:
REGISTER 16-7:
DS70591C-page 234
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-3
bit 2-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
R/W-1
R/W-1
U-0
U-0
—
—
yield unpredictable results.
Unimplemented: Read as ‘0’
PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits
111 = Reserved
110 = Divide by 64, maximum PWM timing resolution
101 = Divide by 32, maximum PWM timing resolution
100 = Divide by 16, maximum PWM timing resolution
011 = Divide by 8, maximum PWM timing resolution
010 = Divide by 4, maximum PWM timing resolution
001 = Divide by 2, maximum PWM timing resolution
000 = Divide by 1, maximum PWM timing resolution (power-on default)
STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits
R/W-1
R/W-1
U-0
U-0
—
—
STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER
STPER: SECONDARY MASTER TIME BASE PERIOD REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
R/W-1
R/W-1
U-0
U-0
—
—
R/W-1
R/W-1
U-0
U-0
Preliminary
—
—
STPER<15:8>
STPER<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
R/W-1
U-0
U-0
—
—
R/W-0
R/W-1
R/W-0
U-0
—
(1)
PCLKDIV<2:0>
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-1
R/W-0
U-0
—
(1)
R/W-0
R/W-1
R/W-0
U-0
—
bit 8
bit 0
bit 8
bit 0