IC MCU AVR32 256KB FLASH 144LQFP

AT32UC3A0256-ALUT

Manufacturer Part NumberAT32UC3A0256-ALUT
DescriptionIC MCU AVR32 256KB FLASH 144LQFP
ManufacturerAtmel
SeriesAVR®32 UC3
AT32UC3A0256-ALUT datasheets
 


Specifications of AT32UC3A0256-ALUT

Core ProcessorAVRCore Size32-Bit
Speed66MHzConnectivityEBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
PeripheralsBrown-out Detect/Reset, POR, PWM, WDTNumber Of I /o109
Program Memory Size256KB (256K x 8)Program Memory TypeFLASH
Ram Size64K x 8Voltage - Supply (vcc/vdd)1.65 V ~ 1.95 V
Data ConvertersA/D 8x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case144-LQFP
Processor SeriesAT32UC3xCoreAVR32
Data Bus Width32 bitData Ram Size64 KB
Interface Type2-Wire, RS-485, SPI, USARTMaximum Clock Frequency66 MHz
Number Of Programmable I/os69Number Of Timers3
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsEWAVR32, EWAVR32-BL, KSK-EVK1100-PLDevelopment Tools By SupplierATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature- 40 CController Family/seriesAT32UC3A
No. Of I/o's109Ram Memory Size64KB
Cpu Speed66MHzNo. Of Timers1
Rohs CompliantYesPackage144LQFP
Device CoreAVR32Family NameAT32
Maximum Speed66 MHzOperating Supply Voltage1.8|3.3 V
For Use WithATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3ALead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
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Features
High Performance, Low Power AVR
– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing 1.49 DMIPS / MHz
Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)
Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State)
– Memory Protection Unit
Multi-hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 15 Peripheral DMA Channels Improves Speed for Peripheral Communication
Internal High-Speed Flash
– 512K Bytes, 256K Bytes, 128K Bytes Versions
– Single Cycle Access up to 33 MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)
External Memory Interface on AT32UC3A0 Derivatives
– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
Interrupt Controller
– Autovectored Low Latency Interrupt Service with Programmable Priority
System Functions
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing
Independant CPU Frequency from USB Frequency
– Watchdog Timer, Real-Time Clock Timer
Universal Serial Bus (USB)
– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
Ethernet MAC 10/100 Mbps interface
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
One Three-Channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities
One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
One Synchronous Serial Protocol Controller
– Supports I2S and Generic Frame-Based Protocols
One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible
One 8-channel 10-bit Analog-To-Digital Converter
16-bit Stereo Audio Bitstream
– Sample Rate Up to 50 KHz
®
32 UC 32-Bit Microcontroller
®
AVR
32
32-Bit
Microcontroller
AT32UC3A0512
AT32UC3A0256
AT32UC3A0128
AT32UC3A1512
AT32UC3A1256
AT32UC3A1128
Preliminary
32058J–AVR32–04/11

AT32UC3A0256-ALUT Summary of contents

  • Page 1

    ... Supports I2S and Generic Frame-Based Protocols • One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible • One 8-channel 10-bit Analog-To-Digital Converter • 16-bit Stereo Audio Bitstream – Sample Rate KHz ® 32-Bit Microcontroller ® AVR 32 32-Bit Microcontroller AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 Preliminary 32058J–AVR32–04/11 ...

  • Page 2

    On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) , 144 BGA (109 GPIO pins) • 5V Input Tolerant I/Os • ...

  • Page 3

    Description The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies MHz. AVR32 high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- ...

  • Page 4

    ... Configuration Summary The table below lists all AT32UC3A memory and package configurations: Device AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 3. Abbreviations • GCLK: Power Manager Generic Clock • GPIO: General Purpose Input/Output • HSB: High Speed Bus • MPU: Memory Protection Unit • ...

  • Page 5

    Blockdiagram Blockdiagram Figure 4- JTAG TDO INTERFACE O[5..0] M SEO[1..0] EVTI_N EVTO_N VBU S D+ USB D - INTERFACE ID VBO ...

  • Page 6

    Processor and architecture 4.1.1 AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture. – 15 general-purpose 32-bit registers. – 32-bit Stack Pointer, Program Counter and Link Register reside in register file. – Fully orthogonal instruction set. – Privileged and ...

  • Page 7

    Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus Figure 4-1 same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies ...

  • Page 8

    Signals Description The following table gives details on the signal name classified by peripheral The signals are multiplexed with GPIO pins as described in on page Signal Description List Table 5-1. Signal Name Function VDDPLL Power supply for PLL ...

  • Page 9

    Signal Description List Table 5-1. Signal Name Function MSEO0 - MSEO1 Trace Frame Control EVTI_N Event In EVTO_N Event Out GCLK0 - GCLK3 Generic Clock Pins RESET_N Reset Pin RTC_CLOCK RTC clock WDTEXT External Watchdog Pin EXTINT0 - EXTINT7 External ...

  • Page 10

    Signal Description List Table 5-1. Signal Name Function ADDR0 - ADDR23 Address Bus CAS Column Signal DATA0 - DATA15 Data Bus NCS0 - NCS3 Chip Select NRD Read Signal NWAIT External Wait Signal NWE0 Write Enable 0 NWE1 Write Enable ...

  • Page 11

    Signal Description List Table 5-1. Signal Name Function RX_DATA SSC Receive Data RX_FRAME_SYNC SSC Receive Frame Sync TX_CLOCK SSC Transmit Clock TX_DATA SSC Transmit Data TX_FRAME_SYNC SSC Transmit Frame Sync A0 Channel 0 Line A A1 Channel 1 Line A ...

  • Page 12

    Signal Description List Table 5-1. Signal Name Function AD0 - AD7 Analog input pins ADVREF Analog positive reference voltage input PWM0 - PWM6 PWM Output Pins DDM USB Device Port Data - DDP USB Device Port Data + VBUS USB ...

  • Page 13

    Power Considerations 6.1 Power Supplies The AT32UC3A has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal. • VDDANA: Powers the ADC Voltage is 3.3V nominal. • VDDIN: Input voltage for the voltage ...

  • Page 14

    Voltage Regulator 6.2.1 Single Power Supply The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be externally connected to ...

  • Page 15

    Analog-to-Digital Converter (A.D.C) reference. The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling. Refer to characteristics. In case ADC is not used, the ADVREF pin should be ...

  • Page 16

    Package and Pinout The device pins are multiplexed with peripheral functions as described in TQFP100 Pinout Figure 7-1. TQFP100 Package Pinout Table 7-1. PB20 1 PB21 2 PB22 3 VDDIO 4 GND 5 PB23 6 PB24 7 PB25 8 ...

  • Page 17

    TQFP100 Package Pinout Table 7-1. PA02 23 PA03 24 PA04 25 LQFP144 Pinout Figure 7-2. VQFP144 Package Pinout Table 7-2. PX00 1 PX01 2 PB20 3 PX02 4 PB21 5 PB22 6 VDDIO 7 GND 8 PB23 9 PX03 10 ...

  • Page 18

    VQFP144 Package Pinout Table 7-2. PB31 22 RESET_N 23 PX05 24 PA00 25 PX06 26 PA01 27 GND 28 VDDCORE 29 PA02 30 PX07 31 PA03 32 PX08 33 PA04 34 PX09 35 VDDIO 36 BGA144 Pinout Figure 7-3. 32058J–AVR32–04/11 ...

  • Page 19

    BGA144 Package Pinout A1..M8 Table 7- VDDIO PB07 A PB08 GND B PB09 PX33 C PB11 PB13 D PB10 VDDIO E PA30 PB14 F TMS PC03 G TDO VDDCORE H TDI PB17 J PC05 PC04 K PB21 GND ...

  • Page 20

    I/O Line Considerations 8.1 JTAG pins TMS, TDI and TCK have pull-up resistors. TDO is an output, driven VDDIO, and has no pull-up resistor. 8.2 RESET_N pin The RESET_N pin is a schmitt input and integrates ...

  • Page 21

    Processor and Architecture This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set and MPU is pre- sented. For further details, see the AVR32 ...

  • Page 22

    A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The ...

  • Page 23

    Figure 9-2. 9.2.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...

  • Page 24

    The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 9-1. Instruction ld.d st.d 9.2.6 Unimplemented instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if ...

  • Page 25

    Programming Model 9.3.1 Register file configuration The AVR32UC register file is shown below. Figure 9-3. Application Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC ...

  • Page 26

    Figure 9-5. Bit 9.3.3 Processor States 9.3.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in page 26. Table 9-2. Priority N/A N/A Mode ...

  • Page 27

    All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described ...

  • Page 28

    Table 9-3. Reg # 33- ...

  • Page 29

    Table 9-3. Reg # 100 101 102 103-191 192-255 9.4 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have ...

  • Page 30

    The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter ...

  • Page 31

    Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated ...

  • Page 32

    Priority and handler addresses for events Table 9-4. Priority Handler Address 1 0x8000_0000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...

  • Page 33

    ... KBytes (AT32UC3A0256, AT32UC3A1256) – 128 KBytes (AT32UC3A1128, AT32UC3A2128) • Internal High-Speed SRAM, Single-cycle access at full speed – 64 KBytes (AT32UC3A0512, AT32UC3A0256, AT32UC3A1512, AT32UC3A1256) – 32KBytes (AT32UC3A1128) 10.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...

  • Page 34

    ... Flash Memory Parameters Table 10-2. Flash Size Part Number (FLASH_PW) AT32UC3A0512 512 Kbytes AT32UC3A1512 512 Kbytes AT32UC3A0256 256 Kbytes AT32UC3A1256 256 Kbytes AT32UC3A1128 128 Kbytes AT32UC3A0128 128 Kbytes 10.3 Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. ...

  • Page 35

    Figure 10-1. HMatrix Master / Slave Connections 32058J–AVR32–04/11 HMATRIX SLAVES CPU Data 0 CPU 1 Instruction CPU SAB 2 PDCA 3 MACB 4 USBB DMA 5 AT32UC3A ...

  • Page 36

    Fuses Settings The flash block contains a number of general purpose fuses. Some of these fuses have defined meanings outside the flash controller and are described in this section. The general purpose fuses are erase by a JTAG chip ...

  • Page 37

    LOCK, EPFL, BOOTPROT These are Flash controller fuses and are described in the FLASHC section. 11.2 Default Fuse Value The devices are shipped with the FGPFRLO register value: 0xFC07FFFF: • GPF31 fuse set to 1b. This fuse is used by ...

  • Page 38

    Peripherals 12.1 Peripheral address map Peripheral Address Mapping Table 12-1. Address 0xE0000000 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFE1800 0xFFFE1C00 0xFFFE2000 0xFFFF0000 0xFFFF0800 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 32058J–AVR32–04/11 Peripheral Name USBB USBB Slave Interface - USBB USBB USBB Configuration ...

  • Page 39

    Peripheral Address Mapping (Continued) Table 12-1. Address 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 12.2 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being ...

  • Page 40

    The following GPIO registers are mapped on the local bus: Table 12-2. Port 32058J–AVR32–04/11 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register ...

  • Page 41

    Table 12-2. Port 3 12.3 Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Inter- rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports groups ...

  • Page 42

    Table 12-3. 32058J–AVR32–04/11 Interrupt Request Signal Map 0 General Purpose Input/Output 1 General Purpose Input/Output 2 General Purpose Input/Output 3 General Purpose Input/Output 4 General Purpose Input/Output 5 General Purpose Input/Output 6 General Purpose Input/Output 2 7 General Purpose Input/Output ...

  • Page 43

    Table 12-3. 12.4 Clock Connections 12.4.1 Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 12-4. Source Internal External 12.4.2 USARTs Each USART can be connected to an internally divided clock: Table ...

  • Page 44

    SPIs Each SPI can be connected to an internally divided clock: Table 12-6. SPI 0 1 12.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of ...

  • Page 45

    Table 12-8. PID Value 12.7 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 3 peripheral functions ...

  • Page 46

    GPIO Controller Function Multiplexing Table 12- PA16 42 60 PA17 43 62 PA18 44 64 PA19 45 66 PA20 51 73 PA21 52 74 PA22 53 75 PA23 54 76 PA24 55 77 PA25 56 78 PA26 57 ...

  • Page 47

    GPIO Controller Function Multiplexing Table 12- PB24 8 13 PB25 9 14 PB26 10 15 PB27 14 19 PB28 15 20 PB29 16 21 PB30 17 22 PB31 63 85 PC00 64 86 PC01 85 124 PC02 86 ...

  • Page 48

    GPIO Controller Function Multiplexing Table 12-9. 99 PX25 101 PX26 103 PX27 105 PX28 107 PX29 110 PX30 112 PX31 114 PX32 118 PX33 120 PX34 135 PX35 137 PX36 140 PX37 142 PX38 144 PX39 12.8 Oscillator Pinout The ...

  • Page 49

    GPIO The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is not available for this device. 12.11 Peripheral overview 12.11.1 External Bus Interface • Optimized for Application Memory Space support • Integrates Two External Memory ...

  • Page 50

    Supports Mobile SDRAM Devices • Error Detection – Refresh Error Interrupt • SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used 12.11.4 USB Controller • USB 2.0 Compliant, Full-/Low-Speed ...

  • Page 51

    Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation ...

  • Page 52

    Ethernet 10/100 MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operations • MII or RMII interface to the physical layer • Register Interface to address, data, ...

  • Page 53

    Power Manager (PM) Rev: 2.0.0.1 13.1 Features • Controls integrated oscillators and PLLs • Generates clocks and resets for digital logic • Supports 2 crystal oscillators 450 kHz-16 MHz • Supports 2 PLLs 80-240 MHz • Supports 32 KHz ...

  • Page 54

    Block Diagram Voltage Regulator Calibration fuses Registers Brown-Out Detector Power-O n Detector External Reset Pad Figure 13-1. Power Manager block diagram 32058J–AVR32–04/11 RCOSC Oscillator 0 PLL0 PLL1 Oscillator 1 OSC/PLL Control signals Oscillator and PLL Control Sleep Controller Interrupts ...

  • Page 55

    Product Dependencies 13.4.1 I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their ...

  • Page 56

    The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared according to the status of the oscillators. A zero ...

  • Page 57

    PLL by two and bring the clock in range of the max frequency of the CPU. When the PLL is switched on, or when changing the clock source or multiplication factor for the PLL, the ...

  • Page 58

    Synchronous clocks The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main clock is divided by ...

  • Page 59

    CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling value, resulting in a CPU clock frequency: f CPU Similarly, the clock for the PBA, and PBB can be divided by writing their respective ...

  • Page 60

    Sleep modes In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle possible to switch off the CPU clock and optionally other clock domains to save power. This ...

  • Page 61

    The power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption. 13.5.7.3 Precautions when entering sleep mode Modules communicating with external circuits should normally be disabled before entering ...

  • Page 62

    Osc0 clock Osc1 clock PLL0 clock PLL1 clock Figure 13-5. Generic clock generation 13.5.8.1 Enabling a generic clock A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator 0 ...

  • Page 63

    Generic clock implementation In AT32UC3A, there are 6 generic clocks. These are allocated to different functions as shown in Table 13-2. Table 13-2. Clock number 13.5.9 Divided PB clocks The clock generator in the Power Manager provides divided PBA ...

  • Page 64

    It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pul- lup, and does not need to be driven externally when negated. reset sources supported by the Reset Controller ...

  • Page 65

    Table 13-4 Effect of the different reset events Table 13-4. CPU/HSB/PBA/PBB (excluding Power Manager) 32 KHz oscillator RTC control register GPLP registers Watchdog control register Voltage Calibration register RC Oscillator Calibration register BOD control register Bandgap control register Clock control ...

  • Page 66

    External Reset The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset. 13.5.12 Calibration registers The Power Manager controls the calibration of the RC oscillator, voltage ...

  • Page 67

    Generic Clock Control 0x0064 - 0x00BC Reserved 0x00C0 RC Oscillator Calibration Register 0x00C4 Bandgap Calibration Register 0x00C8 Linear Regulator Calibration Register 0x00CC Reserved 0x00D0 BOD Level Register 0x00D4 - 0x013C Reserved 0x0140 Reset Cause Register 0x0144 - 0x01FC Reserved ...

  • Page 68

    Main Clock Control MCCTRL Name: Read/Write Access Type • MCSEL: Main Clock Select 0: The slow clock is the source for the main ...

  • Page 69

    Clock Select CKSEL Name: Read/Write Access Type PBBDIV - 23 22 PBADIV - 15 14 HSBDIV - 7 6 CPUDIV - • PBBDIV, PBBSEL: PBB Division and Clock Select PBBDIV = 0: PBB clock equals main clock. ...

  • Page 70

    Clock Mask CPU/HSB/PBA/PBBMASK Name: Read/Write Access Type • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for ...

  • Page 71

    Maskable module clocks in AT32UC3A. Table 13-5. Bit CPUMASK SYSTIMER (COMPARE/COUNT REGISTERS CLK) 31 32058J–AVR32–04/11 HSBMASK PBAMASK - TC - ABDAC - - - - AT32UC3A PBBMASK - - - - 71 ...

  • Page 72

    PLL Control PLL0,1 Name: Read/Write Access Type RESERVED 23 22 RESERVED 15 14 RESERVED • RESERVED: Reserved bitfields Reserved for internal use. Always write to 0. • PLLCOUNT: PLL Count Specifies the number ...

  • Page 73

    PLLOPT Fields Description in AT32UC3A Table 13-6. Description PLLOPT[0]: VCO frequency 0 160MHz<f 1 80MHz<f PLLOPT[1]: Output divider PLLOPT[2] 0 Wide Bandwidth Mode enabled 1 Wide Bandwidth Mode disabled • PLLOSC: PLL Oscillator Select 0: Oscillator ...

  • Page 74

    PM Oscillator 0/1 Control Register name Register access • MODE: Oscillator Mode Choose between crystal, or external clock 0: External clock connected on ...

  • Page 75

    PM 32 KHz Oscillator Control Register Register name Register access Note: This register is only reset by Power-On Reset • OSC32EN: Enable the ...

  • Page 76

    Interrupt Enable/Disable/Mask/Status/Clear IER/IDR/IMR/ISR/ICR Name: IER/IDR/ICR: Write-only Access Type: IMR/ISR: Read-only OSC0RDY MSKRDY • BODDET: Brown out detection Set to 1 when transition ...

  • Page 77

    The effect of writing or reading the bits listed above depends on which register is being accessed: • IER (Write-only effect 1: Enable Interrupt • IDR (Write-only effect 1: Disable Interrupt • IMR (Read-only) 0: Interrupt ...

  • Page 78

    Power and Oscillators Status POSCSR Name: Read-only Access Type OSC0RDY MSKRDY • BODDET: Brown out detection 0: No BOD event 1: BOD has detected that ...

  • Page 79

    Generic Clock Control GCCTRL Name: Read/Write Access Type There is one GCCTRL register per generic clock in the design. • DIV: Division Factor • DIVEN: ...

  • Page 80

    Reset Cause RCAUSE Name: Read-only Access Type CPUERR - • POR Power-on Reset The CPU was reset due to the supply voltage being lower than ...

  • Page 81

    BOD Control BOD Level register Register name Register access HYST • KEY: Register Write protection This field must be written twice, first with key value 0x55, ...

  • Page 82

    RC Oscillator Calibration Register name Register access • CALIB: Calibration Value Calibration Value for the RC oscillator. • FCD: Flash Calibration Done Set to 1 when CTRL, ...

  • Page 83

    Bandgap Calibration Register name Register access • KEY: Register Write protection This field must be written twice, first with key value 0x55, then 0xAA, for ...

  • Page 84

    PM Voltage Regulator Calibration Register Register name Register access • KEY: Register Write protection This field must be written twice, first with key value 0x55, ...

  • Page 85

    General Purpose Low-power register 0/1 Register name Register access These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the content of these ...

  • Page 86

    Real Time Counter (RTC) Rev: 2.3.0.1 14.1 Features • 32-bit real-time counter with 16-bit prescaler • Clocked from RC oscillator or 32 KHz oscillator • High resolution: Max count frequency 16 KHz • Long delays – Max timeout 272 ...

  • Page 87

    Block Diagram Figure 14-1. Real Time Counter module block diagram RTC_CTRL EN CLK32 32 kHz 1 16-bit Prescaler RC OSC 0 14.4 Product Dependencies 14.4.1 Power Management The RTC is continuously clocked, and remains operating in all sleep modes ...

  • Page 88

    The CLK32 bit selects either the RC oscillator or the 32 KHz oscillator as clock source for the prescaler. The PSEL bitfield selects the prescaler tapping, selecting the source clock for the RTC: f RTC 14.5.1.2 Counter operation When enabled, ...

  • Page 89

    User Interface Offset 0x00 0x04 0x08 0x10 RTC Interrupt Enable 0x14 RTC Interrupt Disable 0x18 RTC Interrupt Mask 0x1C RTC Interrupt Status 0x20 RTC Interrupt Clear 14.6.1 RTC Control CTRL Name: Read/Write Access Type ...

  • Page 90

    WAKE_EN: Wakeup enable 0: The RTC does not wake up the CPU from sleep modes 1: The RTC wakes up the CPU from sleep modes. • PCLR: Prescaler Clear Writing 1 to this strobe clears the prescaler. • EN: ...

  • Page 91

    RTC Value VAL Name: Read/Write Access Type • VAL: RTC Value This value is incremented on every rising edge of the source clock. 32058J–AVR32–04/ VAL[31:24 ...

  • Page 92

    RTC Top TOP Name: Read/Write Access Type • TOP: RTC Top Value VAL wraps at this value. 32058J–AVR32–04/ TOP[31:24 TOP[23:16 TOP[15:8] 5 ...

  • Page 93

    RTC Interrupt Enable/Disable/Mask/Status/Clear IER/IDR/IMR/ISR/ICR Name: IER/IDR/ICR: Write-only Access Type: IMR/ISR: Read-only • TOPI: Top Interrupt VAL has wrapped at its top value. The ...

  • Page 94

    Watchdog Timer (WDT) Rev: 2.3.0.1 15.1 Features • Watchdog Timer counter with 16-bit prescaler • Clocked from RC oscillator 15.2 Description The Watchdog Timer (WDT) has a prescaler generating a timeout period. This prescaler is clocked from the RC ...

  • Page 95

    Functional Description The WDT is enabled by writing the EN bit in the CTRL register to one. This also enables the RC clock for the prescaler. The PSEL bitfield in the same register selects the watchdog timeout period: T ...

  • Page 96

    User Interface Offset 0x00 0x04 32058J–AVR32–04/11 Register Register Name WDT Control WDT Clear AT32UC3A Access CTRL Read/Write CLR Write-only Reset 0x0 0x0 96 ...

  • Page 97

    WDT Control CTRL Name: Read/Write Access Type • KEY This bitfield must be written twice, first with key value 0x55, then 0xAA, for a write ...

  • Page 98

    WDT Clear CLR Name: Write-only Access Type: When the watchdog timer is enabled, this register must be periodically written, with any value, within the watchdog timeout period, to prevent a watchdog reset. 32058J–AVR32–04/11 AT32UC3A 98 ...

  • Page 99

    Interrupt Controller (INTC) Rev: 1.0.1.1 16.1 Description The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an inter- rupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for regular, maskable ...

  • Page 100

    All of the input lines in each group are logically-ORed together to form the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group. The Request Masking hardware maps each of the GrpReq lines ...

  • Page 101

    User Interface This chapter lists the INTC registers are accessible through the ...

  • Page 102

    Interrupt Request Registers Register Name: Access Type IRR(32*x+31) IRR(32*x+30) IRR(32*x+29 IRR(32*x+23) IRR(32*x+22) IRR(32*x+21 IRR(32*x+15) IRR(32*x+14) IRR(32*x+13 IRR(32*x+7) IRR(32*x+6) IRR(32*x+5) • IRR: Interrupt Request line interrupt request is pending ...

  • Page 103

    Interrupt Priority Registers Register Name: Access Type INTLEVEL[1: • INTLEVEL: Interrupt level associated with this group Indicates the EVBA-relative offset of the interrupt handler of the corresponding ...

  • Page 104

    Interrupt Cause Registers Register Name: Access Type • CAUSE: Interrupt group causing interrupt of priority n ICRn identifies the group with the highest ...

  • Page 105

    External Interrupts Controller (EIC) Rev: 2.3.0.2 17.1 Features • Dedicated interrupt requests for each interrupt • Individually maskable interrupts • Interrupt on rising or falling edge • Interrupt on high or low level • Asynchronous interrupts for sleep modes ...

  • Page 106

    Block Diagram Figure 17-1. External Interrupt Module block diagram EIM_EN EIM_DIS EXTINTn Enable NMI EIM_CTRL 17.4 Product Dependencies 17.4.1 I/O Lines The External Interrupt and keypad scan pins are multiplexed with PIO lines. To act as external interrupts, these ...

  • Page 107

    Functional Description 17.5.1 External Interrupts To enable an external interrupt EXTINTn must be written register EN. Similarly, writing EXTINTn register DIS disables the interrupt. The status of each Interrupt line can be observed ...

  • Page 108

    The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution mode. Still, as for the other external interrupts, the actual NMI input line can be enabled and dis- abled by accessing the registers ...

  • Page 109

    User Interface Offset 0x00 EIC Interrupt Enable 0x04 EIC Interrupt Disable 0x08 EIC Interrupt Mask 0x0C EIC Interrupt Status 0x10 EIC Interrupt Clear 0x14 External Interrupt Mode 0x18 External Interrupt Edge 0x1C External Interrupt Level 0x20 External Interrupt Filter ...

  • Page 110

    EIC Interrupt Enable/Disable/Mask/Status/Clear IER/IDR/IMR/ISR/ICR Name: IER/IDR/ICR: Write-only Access Type: IMR/ISR: Read-only INT7 INT6 The effect of writing or reading the bits listed above depends on ...

  • Page 111

    External Interrupt Mode/Edge/Level/Filter/Async MODE/EDGE/LEVEL/FILTER/ASYNC Name: Read/Write Access Type INT7 INT6 The bit interpretation is register specific: • MODE 0: Interrupt is edge triggered 1: Interrupt ...

  • Page 112

    External Interrupt Test TEST Name: Read/Write Access Type TEST_EN - INT7 INT6 • NMI If TEST_EN is 1, the value of this bit will be the value ...

  • Page 113

    External Interrupt Scan SCAN Name: Read/Write Access Type • Keypad scanning is disabled 1: Keypad scanning is enabled • PRESC Prescale ...

  • Page 114

    External Interrupt Enable/Disable/Control EN/DIS/CTRL Name: EN/DIS: Write-only Access Type: CTRL: Read-only INT7 INT6 The bit interpretation is register specific: • effect 1: ...

  • Page 115

    Flash Controller (FLASHC) Rev: 2.0.0.2 18.1 Features • Controls flash block with dual read ports allowing staggered reads. • Supports 0 and 1 wait state bus access. • Allows interleaved burst reads for systems with one wait state, outputting ...

  • Page 116

    Functional description 18.4.1 Bus interfaces The FLASHC has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the flash array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands and control ...

  • Page 117

    The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in ure 18-1. Reading the memory space between address pw and 2^21-1 returns an undefined result. The User page is permanently mapped to word address 2^21. ...

  • Page 118

    The page buffer is also used for writes to the User page. Write operations can be prevented by programming the Memory Protection Unit of the CPU. Writing 8-bit and 16-bit data to the page buffer is not allowed and may ...

  • Page 119

    CPU enter sleep mode after writing to FCMD polling FSR for command com- pletion. This polling will result in an access pattern with IDLE HSB cycles. All the commands are protected by the same keyword, which ...

  • Page 120

    Lock Error: The page to be programmed belongs to a locked region. A command must be executed to unlock the corresponding region before programming can start. 18.5.2 Erase All operation The entire memory is erased if the Erase All ...

  • Page 121

    Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.: Table 18-2. General- Purpose fuse number 15:0 16 19:17 The BOOTPROT fuses protects the following ...

  • Page 122

    An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse Byte (PGPFB) instruction. A PGPFB to GP fuse byte ...

  • Page 123

    User interface 18.8.1 Address map The following addresses are used by the FLASHC. All offsets are relative to the base address allocated to the flash controller. Table 18-4. Offset 0x0 0x4 0x8 0xc 0x10 (*) The value of the ...

  • Page 124

    Flash Control Register (FCR) Offset: 0x0 FWS FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates ...

  • Page 125

    Flash Command Register (FCMD) Offset: 0x4 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit to ...

  • Page 126

    PAGEN: Page number The PAGEN field is used to address a page or fuse bit for certain operations. In order to sim- plify programming, the PAGEN field is automatically updated every time the page buffer is written to. For every ...

  • Page 127

    Flash Status Register (FSR) Offset: 0x08 31 30 LOCK15 LOCK14 23 22 LOCK7 LOCK6 15 14 FSZ FRDY: Flash Ready Status 0: The flash controller is busy and the application must wait before running a ...

  • Page 128

    FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 18-7. FSZ LOCKx: Lock Region x Lock Status 0: The ...

  • Page 129

    Flash General Purpose Fuse Register High (FGPFRHI) Offset: 0x0C 31 30 GPF63 GPF62 23 22 GPF55 GPF54 15 14 GPF47 GPF46 7 6 GPF39 GPF38 This register is only used in systems with more than 32 GP fuses. GPFxx: ...

  • Page 130

    Flash General Purpose Fuse Register Low (FGPFRLO) Offset: 0x10 31 30 GPF31 GPF30 23 22 GPF23 GPF22 15 14 GPF15 GPF14 7 6 GPF07 GPF06 GPFxx: General Purpose Fuse xx 0: The fuse has a written/programmed state. 1: The ...

  • Page 131

    AT32UC3A 131 ...

  • Page 132

    HSB Bus Matrix (HMATRIX) Rev: 2.3.0.1 19.1 Features • User Interface on peripheral bus • Configurable Number of Masters (Up to sixteen) • Configurable Number of Slaves (Up to sixteen) • One Decoder for Each Master • Three Different ...

  • Page 133

    No Default Master At the end of the current access other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode. 19.4.2 Last Access Master At the end of the current ...

  • Page 134

    Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. page 134. 19.5.1.1 Undefined Length Burst Arbitration In order to avoid long slave ...

  • Page 135

    Round-Robin Arbitration with Last Default Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. In fact, at ...

  • Page 136

    User Interface Register Mapping Table 19-1. Offset Register 0x0000 Master Configuration Register 0 0x0004 Master Configuration Register 1 0x0008 Master Configuration Register 2 0x000C Master Configuration Register 3 0x0010 Master Configuration Register 4 0x0014 Master Configuration Register 5 0x0018 ...

  • Page 137

    Register Mapping (Continued) Table 19-1. Offset Register 0x008C Priority Register B for Slave 1 0x0090 Priority Register A for Slave 2 0x0094 Priority Register B for Slave 2 0x0098 Priority Register A for Slave 3 0x009C Priority Register B for ...

  • Page 138

    Register Mapping (Continued) Table 19-1. Offset Register 0x0124 Special Function Register 5 0x0128 Special Function Register 6 0x012C Special Function Register 7 0x0130 Special Function Register 8 0x0134 Special Function Register 9 0x0138 Special Function Register 10 0x013C Special Function ...

  • Page 139

    Bus Matrix Master Configuration Registers MCFG0...MCFG15 Register Name: Read/Write Access Type – – – – – – – – • ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted ...

  • Page 140

    Bus Matrix Slave Configuration Registers SCFG0...SCFG15 Register Name: Read/Write Access Type – – – – – – • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit ...

  • Page 141

    Bus Matrix Priority Registers A For Slaves PRAS0...PRAS15 Register Name: Read/Write Access Type M7PR 23 22 M5PR 15 14 M3PR 7 6 M1PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected ...

  • Page 142

    Bus Matrix Priority Registers B For Slaves PRBS0...PRBS15 Register Name: Read/Write Access Type M15PR 23 22 M13PR 15 14 M11PR 7 6 M9PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected ...

  • Page 143

    Bus Matrix Master Remap Control Register MRCR Register Name: Read/Write Access Type: 0x0000_0000 Reset – – – – RCB15 RCB14 7 6 RCB7 RCB6 • RCB: Remap Command Bit for Master x 0: ...

  • Page 144

    Bus Matrix Special Function Registers SFR0...SFR15 Register Name: Read/Write Access Type: Reset • SFR: Special Function Register Fields The bitfields of these registers are described in the Peripherals chapter. 32058J–AVR32–04/11 29 ...

  • Page 145

    ... External Bus Interface (EBI) Rev: 1.0.0.1 20.1 Features • Present only on AT32UC3A0512 and AT32UC3A0256 • Optimized for Application Memory Space support • Integrates Two External Memory Controllers: – Static Memory Controller – SDRAM Controller • Optimized External Bus: – 16-bit Data Bus – ...

  • Page 146

    Block Diagram 20.3.1 External Bus Interface Figure 20-1 Figure 20-1. Organization of the External Bus Interface 32058J–AVR32–04/11 shows the organization of the External Bus Interface. AT32UC3A 146 ...

  • Page 147

    I/O Lines Description EBI I/O Lines Description Table 20-1. Name Function D0 - D15 Data Bus A0 - A23 Address Bus NWAIT External Wait Signal NCS0 - NCS3 Chip Select Lines NWR0 - NWR3 Write Signals NOE Output Enable ...

  • Page 148

    Table 20-2. A[22:15] A[23] D[15:0] 20.5 Application Example 20.5.1 Hardware Interface Table 20-3 on page 148 external devices for each Memory Controller. Table 20-3. Signals Controller D15 A0/NBS0 A1/NWR2/NBS2 A2 - A22 A23 NCS0 NCS1/SDCS0 ...

  • Page 149

    Table 20-4. Signals Controller D0 - D15 A0/NBS0 A1/NWR2/NBS2 A2 - A10 A11 SDA10 A12 A13 - A14 A15 A16/BA0 A17/BA1 A18 - A23 NCS0 NCS1/SDCS0 NCS2 NCS2 NCS3 NRD/NOE NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK SDCKE RAS CAS SDWE NWAIT 32058J–AVR32–04/11 ...

  • Page 150

    Connection Examples Figure 20-2 Figure 20-2. EBI Connections to Memory Devices 32058J–AVR32–04/11 shows an example of connections between the EBI and external devices. EBI D0-D15 RAS CAS SDRAM SDCK D0-D7 SDCKE D0-D7 SDWE A0/NBS0 CS NWR1/NBS1 ...

  • Page 151

    Product Dependencies 20.6.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the GPIO lines. The programmer must first program the GPIO controller to assign the External Bus Interface pins to their peripheral ...

  • Page 152

    Static Memory Controller For information on the Static Memory Controller, refer to the Static Memory Controller Section. 20.7.4 SDRAM Controller For information on the SDRAM Controller, refer to the SDRAM Section. 32058J–AVR32–04/11 AT32UC3A 152 ...

  • Page 153

    Peripheral DMA Controller (PDCA) rev: 1.0.0.0 21.1 Features • Generates Transfers to/from Peripherals such as USART, SSC and SPI • Two address pointers/counters per channel allowing double buffering 21.2 Overview The Peripheral DMA controller (PDCA) transfers data between on-chip ...

  • Page 154

    Block Diagram 21.4 Functional Description 21.4.1 Configuration Each channel in the PDCA has a set of configuration registers. Among these are the Memory Address Register (MAR), the Peripheral Select Register (PSR) and the Transfer Counter Regis- ter (TCR). The ...

  • Page 155

    The address will be increased by either depending on the size of the DMA transfer (Byte, Half-Word or Word). The Memory Address Register can be read at any time dur- ing transfer. 21.4.3 Transfer Counter ...

  • Page 156

    Priority If more then one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel 0 the highest ...

  • Page 157

    Offset 0x24 Interrupt Disable Register 0x28 Interrupt Mask Register 0x2C Interrupt Status Register 32058J–AVR32–04/11 Register Register Name AT32UC3A Access IDR Write-only IMR Read-only ISR Read-only Reset - 0x00000000 0x00000000 157 ...

  • Page 158

    PDCA Memory Address Register MAR Name: Read/Write Access Type • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when ...

  • Page 159

    PDCA Peripheral Select Register PSR Name: Read/Write Access Type • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA ...

  • Page 160

    Transfer Counter Register TCR Name: Read/Write Access Type • TCV: Transfer Counter Value Number of data items to be transferred by PDCA. TCV must be programmed with ...

  • Page 161

    PDCA Memory Address Reload Register MARR Name: Read/Write Access Type • MARV: Memory Address Reload Value Reload Value for the Memory Address Register (MAR). This value will be loaded into MAR ...

  • Page 162

    PDCA Transfer Counter Reload Register TCRR Name: Read/Write Access Type • TCRV: Transfer Counter Reload Value Reload value for the Transfer Counter Register (TCR). When TCR reaches ...

  • Page 163

    PDCA Control Register CR Name: Write-only Access Type • ECLR: Error Clear Effect Clear Transfer Error (TERR) flag ...

  • Page 164

    PDCA Mode Register MR Name: Read/Write Access Type • SIZE: Size of transfer SIZE Size of Transfer 0 0 Byte 0 1 Half-Word ...

  • Page 165

    PDCA Status Register SR Name: Read Access Type • TEN: Transfer Enabled 0 = Transfer is disabled for the DMA channel 1 = ...

  • Page 166

    PDCA Interrupt Enable Register IER Name: Write-only Access Type • TERR: Transfer Error effect Enable Transfer Error interrupt. ...

  • Page 167

    PDCA Interrupt Disable Register IDR Name: Write-only Access Type • TERR: Transfer Error effect Disable Transfer Error interrupt. ...

  • Page 168

    PDCA Interrupt Mask Register IMR Name: Read-only Access Type • TERR: Transfer Error 0 = Transfer Error interrupt is disabled Transfer ...

  • Page 169

    PDCA Interrupt Status Register ISR Name: Read-only Access Type • TERR: Transfer Error transfer errors have occurred ...

  • Page 170

    General-Purpose Input/Output Controller (GPIO) Rev. 1.1.0.2 22.1 Features Each I/O line of the GPIO features: • Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line. • A glitch filter providing rejection of pulses shorter than one clock cycle. ...

  • Page 171

    Number of I/O pins. • Functions implemented on each pin. • Peripheral function(s) multiplexed on each I/O pin. • Reset state of registers. 22.3.2 Interrupt Lines The GPIO interrupt lines are connected to the interrupt controller. Using the GPIO ...

  • Page 172

    I/O Line or Peripheral Function Selection When a pin is multiplexed with one or more peripheral functions, the selection is controlled with the register GPER bit in the register is set, the corresponding pin is controlled by ...

  • Page 173

    Figure 22-2. Output line timings Write GPIO_OVR to 1 Write GPIO_OVR to 0 GPIO_OVR / I/O Line 22.4.7 Interrupts The GPIO can be programmed to generate an interrupt when it detects an input change on an I/O line. The module ...

  • Page 174

    Figure 22-3. Interrupt timing with glitch filter disabled clock Pin Level GPIO_IFR The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter is enabled. For the pulse to be registered, it must be sampled ...

  • Page 175

    General Purpose Input/Output (GPIO) User Interface The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32- bit ports that are configurable through an PB interface. Each port has a set of configuration ...

  • Page 176

    GPIO Register Map Table 22-2. Offset Register 0x14 Peripheral Mux Register 0 0x18 Peripheral Mux Register 0 0x1C Peripheral Mux Register 0 0x20 Peripheral Mux Register 1 0x24 Peripheral Mux Register 1 0x28 Peripheral Mux Register 1 0x2C Peripheral Mux ...

  • Page 177

    GPIO Register Map Table 22-2. Offset Register 0xA0 Interrupt Mode Register 0 0xA4 Interrupt Mode Register 0 0xA8 Interrupt Mode Register 0 0xAC Interrupt Mode Register 0 0xB0 Interrupt Mode Register 1 0xB4 Interrupt Mode Register 1 0xB8 Interrupt Mode ...

  • Page 178

    GPIO Enable Register GPER Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-P31: GPIO Enable peripheral function controls the corresponding ...

  • Page 179

    Peripheral Mux Register 0 PMR0 Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Peripheral Multiplexer Select bit 0 22.5.4 Peripheral Mux Register ...

  • Page 180

    Output Driver Enable Register ODER Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Output Driver Enable 0 = The output driver is ...

  • Page 181

    Output Value Register OVR Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Output Value 0 = The value to be driven on ...

  • Page 182

    Pin Value Register PVR Name: Read Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Pin Value 0 = The I/O line is at level ‘0’ The ...

  • Page 183

    Pull-up Enable Register PUER Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Pull-up Enable 0 = The internal pull-up resistor is disabled ...

  • Page 184

    Open Drain Mode Enable Register ODMER Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Open Drain Mode Enable 0 = Open drain ...

  • Page 185

    Interrupt Enable Register IER Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Interrupt Enable 0 = Interrupt is disabled for the corresponding ...

  • Page 186

    Interrupt Mode Register 0 IMR0 Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Interrupt Mode Bit 0 22.5.12 Interrupt Mode Register 1 ...

  • Page 187

    Glitch Filter Enable Register GFER Name: Read, Write, Set, Clear, Toggle Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Glitch Filter Enable 0 = Glitch filter is disabled ...

  • Page 188

    Interrupt Flag Register IFR Name: Read, Clear Access P31 P30 23 22 P23 P22 15 14 P15 P14 • P0-31: Interrupt Flag interrupt condition has been detected on the corresponding ...

  • Page 189

    Programming Examples 22.6.1 8-bit LED-Chaser loop assumed in this example that a subroutine "delay" exists that returns after a given time. 22.6.2 Configuration of USART pins The example below shows how to configure a peripheral module to ...

  • Page 190

    R1, 0x0000 orh R1, 0x0003 st.w R0[AVR32_GPIO_ODERC Make the GPIO control the pins st.w R0[AVR32_GPIO_GPERS Select peripheral B on PC16-PC17 st.w R0[AVR32_GPIO_PMR0S], R1 st.w R0[GPIO_PMR1C Enable peripheral control st.w R0[AVR32_GPIO_GPERC], R1 AT32UC3A ...

  • Page 191

    Serial Peripheral Interface (SPI) Rev: 1.9.9.3 23.1 Features • Supports Communication with Serial External Devices – Four Chip Selects with External Decoder Support Allow Communication with Peripherals – Serial Memories, such as DataFlash and 3-wire EEPROMs ...

  • Page 192

    Block Diagram Figure 23-1. Block Diagram eral Bus Power Manager 32058J–AVR32–04/11 PDC MCK SPI Interface DIV Interrupt Control MCK (1) 32 SPI Interrupt AT32UC3A SPCK MISO MOSI PIO NPCS0/NSS NPCS1 NPCS2 NPCS3 192 ...

  • Page 193

    Application Block Diagram Figure 23-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master 32058J–AVR32–04/11 SPCK MISO MOSI NPCS0 NPCS1 NPCS2 NC NPCS3 AT32UC3A SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave ...

  • Page 194

    Signal Description Table 23-1. Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS 32058J–AVR32–04/11 Signal Description Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select AT32UC3A Type Master Slave Input Output ...

  • Page 195

    Product Dependencies 23.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. To use ...

  • Page 196

    Functional Description 23.7.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are ...

  • Page 197

    Figure 23-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI MSB (from master) MISO MSB (from slave) NSS (to slave) * Not defined, but ...

  • Page 198

    Master Mode Operations When configured in Master Mode, the SPI uses the internal programmable baud rate generator as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives ...

  • Page 199

    Master Mode Block Diagram Figure 23-5. Master Mode Block Diagram MCK MCK/N MISO NPCS0 32058J–AVR32–04/11 FDIV SPI_CSR0..3 SCBR 0 Baud Rate Generator 1 SPI_CSR0..3 BITS NCPHA CPOL LSB SPI_CSR0..3 PS PCSDEC SPI_MR PCS 0 SPI_TDR PCS 1 MSTR AT32UC3A ...

  • Page 200

    Master Mode Flow Diagram Figure 23-6. Master Mode Flow Diagram S 32058J–AVR32–04/11 SPI Enable 1 TDRE ? 0 1 CSAAT ? 0 Fixed peripheral Variable 1 peripheral NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS) Delay DLYBS Serializer ...