DSPIC30F6014-30I/PF Microchip Technology, DSPIC30F6014-30I/PF Datasheet - Page 139

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DSPIC30F6014-30I/PF

Manufacturer Part Number
DSPIC30F6014-30I/PF
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F6014-30I/PF

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
144KB
Supply Voltage Range
2.5V To 5.5V
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
3-Wire/AC97/CAN/I2C/I2S/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1DM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F601430IPF

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19.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing until the next sampling trigger. The ADCBUF will not
be updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
If the clearing of the ADON bit coincides with an auto-
start, the clearing has a higher priority and a new
conversion will not start.
19.6
The ADC conversion requires 14 T
the ADC conversion clock is software selected, using a
six-bit counter. There are 64 possible options for T
EQUATION 19-1:
© 2006 Microchip Technology Inc.
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the ADC Conversion
Clock
T
AD
= T
CY
* (0.5 * (ADCS<5:0> + 1))
CLOCK
ADC CONVERSION
AD
. The source of
dsPIC30F6011/6012/6013/6014
AD
.
The internal RC oscillator is selected by setting the
ADRC bit.
For correct ADC conversions, the ADC conversion
clock (T
time of 334 nsec (for V
Specifications section for minimum T
operating conditions.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1:
Since,
Sampling Time = Acquisition Time + Conversion Time
Therefore,
Sampling Rate =
If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
Therefore,
Set ADCS<5:0> = 19
AD
ADCS<5:0> = 2
Minimum T
) must be selected to ensure a minimum T
Actual T
= ~200 kHz
= 1 T
= 15 x 334 nsec
AD
T
(15 x 334 nsec)
AD
CY
AD
= 2 •
= 19.04
=
=
= 334 nsec
ADC CONVERSION
CLOCK AND SAMPLING
RATE CALCULATION
DD
= 334 nsec
= 33 .33 nsec (30 MIPS)
+ 14 T
T
33.33 nsec
1
= 5V). Refer to the Electrical
T
T
CY
2
AD
33.33 nsec
CY
334 nsec
2
AD
(ADCS<5:0> + 1)
– 1
DS70117F-page 137
(19 + 1)
AD
– 1
under other
AD

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