DSPIC30F6014-30I/PF Microchip Technology, DSPIC30F6014-30I/PF Datasheet - Page 48

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DSPIC30F6014-30I/PF

Manufacturer Part Number
DSPIC30F6014-30I/PF
Description
IC DSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F6014-30I/PF

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
144KB
Supply Voltage Range
2.5V To 5.5V
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
3-Wire/AC97/CAN/I2C/I2S/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F601430IPF

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dsPIC30F6011/6012/6013/6014
5.1
The user assignable interrupt priority (IP<2:0>) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble within the IPCx regis-
ter(s). Bit 3 of each nibble is not used and is read as a
‘0’. These bits define the priority level assigned to a
particular interrupt by the user.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC device and their associated
vector numbers.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Low-
Voltage Detect) can be given a priority of 7. The INT0
(External Interrupt 0) may be assigned to priority level
1, thus giving it a very low effective priority.
DS70117F-page 46
Note:
Note 1: The natural order priority scheme has 0
2: The natural order priority number is the
Interrupt Priority
The user selectable priority levels start at
0 as the lowest priority and level 7 as the
highest priority.
as the highest priority and 53 as the
lowest priority.
same as the INT number.
TABLE 5-1:
Highest Natural Order Priority
Lowest Natural Order Priority
Number
39-40
43-53
INT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
41
42
0
1
2
3
4
5
6
7
8
9
Number
Vector
47-48
51-61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
49
50
8
9
INTERRUPT VECTOR TABLE
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer 1
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer 2
T3 – Timer 3
SPI1
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Convert Done
NVM – NVM Write Complete
SI2C – I
MI2C – I
Input Change Interrupt
INT1 – External Interrupt 1
IC7 – Input Capture 7
IC8 – Input Capture 8
OC3 – Output Compare 3
OC4 – Output Compare 4
T4 – Timer 4
T5 – Timer 5
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
SPI2
C1 – Combined IRQ for CAN1
IC3 – Input Capture 3
IC4 – Input Capture 4
IC5 – Input Capture 5
IC6 – Input Capture 6
OC5 – Output Compare 5
OC6 – Output Compare 6
OC7 – Output Compare 7
OC8 – Output Compare 8
INT3 – External Interrupt 3
INT4 – External Interrupt 4
C2 – Combined IRQ for CAN2
Reserved
DCI – Codec Transfer Done
LVD – Low-Voltage Detect
Reserved
© 2006 Microchip Technology Inc.
2
Interrupt Source
2
C Slave Interrupt
C Master Interrupt

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