Z8F3222AR020SG Zilog, Z8F3222AR020SG Datasheet - Page 120

• Manufacturer Part Number: Z8F3222AR020SG
• Description: IC ENCORE MCU FLASH 32K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F3222AR020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z8F322x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4261; Z8F3222AR020SG

PS019921-0308
External Driver Enable
configuration bits. In general, the address compare feature reduces the load on the CPU,
since it does not need to access the UART when it receives data directed to other devices
on the multi-node network. The following three MULTIPROCESSOR modes are avail-
able in hardware:
•
•
•
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all
MULTIPROCESSOR modes, bit MPEN of the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. At this point, each new
incoming byte interrupts the CPU. The software is then responsible for determining the
end of the frame. It checks for end-of-frame by reading the MPRX bit of the UART Status
1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of
this new frame is different from the UART’s address, then set MPMD[0] to 1 causing the
UART interrupts to go inactive until the next address byte. If the new frame’s address
matches the UART’s, the data in the new frame is processed as well.
The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART’s
address into the UART Address Compare Register. This mode introduces more hardware
control, interrupting only on frames that match the UART’s address. When an incoming
address byte does not match the UART’s address, it is ignored. All successive data bytes in
this frame are also ignored. When a matching address byte occurs, an interrupt is issued
and further interrupts now occur on each successive data byte. The first data byte in the
frame contains the NEWFRM=1 in the UART Status 1 Register. When the next address byte
occurs, the hardware compares it to the UART’s address. If there is a match, the interrupts
continue sand the NEWFRM bit is set for the first byte of the new frame. If there is no
match, then the UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame is still accompanied by a NEWFRM assertion.
The UART provides a Driver Enable (
reduces the software overhead associated with using a GPIO pin to control the transceiver
when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and Stop bits as displayed in
Interrupt on all address bytes.
Interrupt on matched address bytes and correctly framed data bytes.
Interrupt only on correctly framed data bytes.
DE
) signal for off-chip bus transceivers. This feature
Figure
16. The Driver Enable signal asserts
Z8 Encore! XP
Product Specification
®
F64XX Series
UART
106