Z8F3222AR020SG Zilog, Z8F3222AR020SG Datasheet - Page 151

• Manufacturer Part Number: Z8F3222AR020SG
• Description: IC ENCORE MCU FLASH 32K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F3222AR020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z8F322x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4261; Z8F3222AR020SG

Table 67. SPI Diagnostic State Register (SPIDST)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
SPI Diagnostic State Register
SCKEN
7
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave.
The SPI Diagnostic State register
is a read only register used for SPI diagnostics.
SCKEN—Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next
TCKEN—Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the
SPISTATE—SPI State Machine
Defines the current state of the internal SPI State Machine.
system clock)
serial data out is updated on the next system clock (MOSI or MISO).
TCKEN
6
5
(Table
4
F64H
67) provides observability of internal state. This
R
0
3
SPISTATE
Z8 Encore! XP
2
Product Specification
Serial Peripheral Interface
1
®
F64XX Series
0
137