Z8F3222AR020SG Zilog, Z8F3222AR020SG Datasheet - Page 122

• Manufacturer Part Number: Z8F3222AR020SG
• Description: IC ENCORE MCU FLASH 32K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F3222AR020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z8F322x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4261; Z8F3222AR020SG

PS019921-0308
Note:
In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
•
•
•
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status 0 register is updated to indicate the
overrun condition (and Break Detect, if applicable). The
the Receive Data register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and should be ignored. The
cates if the overrun was caused by a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data register must be read again to clear the
error bits is the UART Status 0 register. Updates to the Receive Data register occur only
when the next data word is received.
UART Data and Error Handling Procedure
Figure 17
interrupt service routines.
A data byte has been received and is available in the UART Receive Data register.
This interrupt can be disabled independent of the other receiver interrupt sources. The
received data interrupt occurs once the receive character has been received and placed
in the Receive Data register. Software must respond to this received data available
condition before the next character is completely received to avoid an overrun error.
A break is received
An overrun is detected
A data framing error is detected
on page 109 displays the recommended procedure for use in UART receiver
Z8 Encore! XP
RDA
bit is set to 1 to indicate that
Product Specification
®
F64XX Series
BRKD
bit indi-
UART
108