Z8F3222AR020SG Zilog, Z8F3222AR020SG Datasheet - Page 48

• Manufacturer Part Number: Z8F3222AR020SG
• Description: IC ENCORE MCU FLASH 32K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F3222AR020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z8F322x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4261; Z8F3222AR020SG

SPI Data
SPIDATA (F60H - Read/Write)
SPI Control
SPICTL (F61H - Read/Write)
PS019921-0308
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SPI Data [7:0]
SPI Enable
0 = SPI disabled
1 = SPI enabled
Master Mode Enabled
0 = SPI configured in Slave mode
1 = SPI configured in Master mode
Wire-OR (open-drain) Mode
0 = SPI signals not configured for
1 = SPI signals (SCK, SS, MISO,
and
drain
Clock Polarity
0 = SCK idles Low
1 = SPI idles High
Phase Select
Sets the phase relationship of the
data
to the clock.
BRG Timer Interrupt Request
0 = BRG timer function is disabled
1 = BRG time-out interrupt is
enabled
Start an SPI Interrupt Request
0 = No effect
1 = Generate an SPI interrupt
request
Interrupt Request Enable
0 = SPI interrupt requests are
disabled
1 = SPI interrupt requests are
enabled
open-drain
MOSI) configured for open-
SPI Status
SPISTAT (F62H - Read Only)
SPI Mode
SPIMODE (F63H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Z8 Encore! XP
Slave Select
0 = If Slave, SS pin is asserted
1 = If Slave, SS pin is not asserted
Transmit Status
0 = No data transmission in progress
1 = Data transmission now in
progress
Reserved
Slave Mode Transaction Abort
0 = No slave mode transaction abort
1 = Slave mode transaction abort
was
Collision
0 = No multi-master collision
detected
1 = Multi-master collision was
detected
Overrun
0 = No overrun error detected
1 = Overrun error was detected
Interrupt Request
0 = No SPI interrupt request pending
1 = SPI interrupt request is pending
Slave Select Value
Slave Select I/O
Number of Data Bits Per Character
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bit
110 = 6 bits
If Master and SPIMODE[1] = 1:
0 = SS pin driven Low
1 = SS pin driven High
0 = SS pin configured as an input
1 = SS pin configured as an output
Product Specification
detected
detected
(Master mode only)
Control Register Summary
®
F64XX Series
34