MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 200
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Central Processing Unit
When a floating-point exception is taken, instruction execution resumes at offset 0x0E00 from the base
address indicated by MSR[IP].
3.15.4.13 Implementation-Dependent Software Emulation Exception (0x1000)
An implementation-dependent software emulation exception occurs in the following instances:
Table 3-34
3-56
1
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
When executing any non-implemented instruction. This includes all illegal and unimplemented
optional instructions and all floating-point instructions.
When executing a mtspr or mfspr instruction that specifies an un-implemented
internal-to-the-processor SPR, regardless of the value of bit 0 of the SPR.
When executing a mtspr or mfspr that specifies an un-implemented external-to-the-processor
register and SPR0 = 0 or MSR[PR] = 0 (no program interrupt condition).
shows the register settings set when a software emulation exception occurs.
Register Name
Register Name
Table 3-33. Register Settings following Floating-Point Assist Exceptions
Table 3-34. Register Settings following a Software Emulation Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
10:15
Other
Other
10:15
Other
Bits
Bits
ME
1:4
1:4
LE
All
IP
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
interrupt
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
No change
Cleared to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
Description
Description
Freescale Semiconductor
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