MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 926

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Development Support
comparator when working in half-word mode and to the correct bytes of the data comparator when
working in byte mode.
Since bytes and half-words can be accessed using a larger data width instruction, it is impossible to predict
the exact value of the L-address lines when the requested byte/half-word is accessed, (e.g., if the matched
byte is byte two of the word and it is accessed using a load word instruction), the L-address value will be
of the word (byte zero). Therefore, the CPU masks the two least-significant bits of the L-address
comparators whenever a word access is performed and the least-significant bit whenever a half-word
access is performed.
Address range is supported only when aligned according to the access size. (See
“Examples”).
23.2.1.3
23-12
•
•
A fully supported scenario:
— Looking for:
— Programming options:
— Result:
A fully supported scenario:
— Looking for:
— Programming option:
— Result:
Data size: Byte
Address: 0x00000003
Data value: greater than 0x07 and less than 0x0c
One L-address comparator = 0x00000003 and program for equal
One L-data comparator = 0x00000007 and program for greater than
One L-data comparator = 0x0000000c and program for less than
Both byte masks = 0xe
Both L-data comparators program to byte mode
The event will be correctly detected regardless of the load/store instruction the compiler
chooses for this access
Data size: half-word
Address: greater than 0x00000000 and less than 0x0000000c
Data value: greater than 0x4e204e20 and less than 0x9c409c40
One L-address comparator = 0x00000000 and program for greater than
One L-address comparator = 0x0000000c and program for less than
One L-data comparator = 0x4e204e20 and program for greater than
One L-data comparator = 0x9c409c40 and program for less than
Both byte masks = 0x0
Both L-data comparators program to half-word mode
The event will be correctly detected as long as the compiler does not use a load/store instruction
with data size of byte.
Examples
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 23.2.1.3,
Freescale Semiconductor