MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 393

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

9.5.13
When the MPC561/MPC563 is in slave mode, external master access to the MPC561/MPC563 internal
bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to
be executed. The RETRY signal functions as an output that signals the external master to release the bus
ownership and retry the access after one clock.
Figure 9-39
external access is retried and a pending internal-to-external access follows.
Freescale Semiconductor
CLKOUT
BR (input)
BG
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
Figure 9-38. Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States)
TS (input)
Data
TA (output)
Contention Resolution on External Bus
describes the flow of an external master retried access.
MPC561/MPC563 Reference Manual, Rev. 1.2
O
O
Receive Bus Grant and Bus Busy Negated
Use the Internal Arbiter
O
O
Assert BB, Drive Address and Assert TS
Minimum 2 Wait States
Figure 9-40
Data is sampled
shows the timing when an
External Bus Interface
O
9-53