MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 452

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

L-Bus to U-Bus Interface (L2U)
11.8.6
The L2U global region attribute register (L2U_GRA) defines the protection attributes associated with the
memory region which is not protected under the four DMPU regions. This register also provides
enable/disable control for the four DMPU regions.
11-16
20:21
22:24
26:31
Bits
Bits
25
Reset
Reset
0
1
2
Field ENR0 ENR1 ENR2 ENR3
Field
Addr
Global Region Attribute Register (L2U_GRA)
MSB
16
Name
Name
ENR0
ENR1
ENR2
0
PP
—
—
G
17
1
Figure 11-7. L2U Global Region Attribute Register (L2U_GRA)
Protection bits
00 No supervisor access, no user access
01 Supervisor read/write access, no user access
10 Supervisor read/write access, user read-only access
11 Supervisor read/write access, user read/write access
Reserved
Guarded attribute
0 Not guarded from speculative accesses
1 Guarded from speculative accesses
Reserved
Enable attribute for region 0
0 Region attribute is off
1 Region attribute is on
Enable attribute for region 1
0 Region attribute is off
1 Region attribute is on
Enable attribute for region 2
0 Region attribute is off
1 Region attribute is on
—
18
2
Table 11-9. L2U_RAx Bit Descriptions (continued)
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 11-10. L2U_GRA Bit Descriptions
20
4
PP
21
5
0000_0000_0000_0000
0000_0000_0000_0000
22
6
SPR 536
—
23
7
Description
Description
24
8
25
G
9
—
10
26
11
27
12
28
Freescale Semiconductor
—
13
29
14
30
LSB
15
31