MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 301

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

7.5.3
When a soft reset event occurs, the MPC561/MPC563 reconfigures the development port. Refer to
Chapter 23, “Development
Freescale Semiconductor
1
2
3
4
24:25
26:27
28:30
Bit 15 always comes from the internal Flash Reset Configuration Word (MPC563 only).
This bit should not be set on the MPC561/MPC562.
This bit is HC if read from the internal Flash Reset Configuration Word. See
Word
Available only on the MPC562/MPC564, software should write "0" to this bit for MPC561/MPC563.
Bits
31
(UC3FCFIG)."
Soft Reset Configuration
OERC
Name
DME
ISB
—
Other Exceptions Relocation Control — These bits effect only if ETRE was enabled. See
Table
00 Offset 0
01 Offset 64 Kbytes
10 Offset 512 Kbytes
11 Offset to 0x003F E000
Reserved
Internal Space Base Select — This field defines the initial value of the ISB field in the IMMR
register. A detailed description is in
is mapped to start at address 0x0000_0000. This bit must not be high in the reset configuration
word.
Dual Mapping Enable — This bit determines whether Dual mapping of the internal Flash is
enabled. For a detailed description refer to
disabled.
0 Dual mapping disabled
1 Dual mapping enabled
4-2. Relocation offset:
Support,” for details.
Table 7-5. RCW Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
6-12. The default state is that the internal memory map
Description
Table
10-11. The default state is that dual mapping is
Section 21.2.3.1, “Reset Configuration
Reset
7-13