MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 976

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

READI Module
24.6
The READI registers do not follow the recommendations of the IEEE-ISTO 5001 - 1999, but are loosely
based on the 0.9 release of the standard. See
READI registers are classified into two categories: user-mapped register and tool-mapped registers.
User-mapped register (a memory-mapped register):
Tool-mapped registers (registers which can be accessed only through the development tool and are not
memory mapped):
24.6.1
READI registers are accessible via the auxiliary port. They can be classified into two categories:
user-mapped registers and tool-mapped registers.
24.6.1.1
The operating system writes the ID for the current task/process in the single user-mapped register, the
READI ownership trace (OTR) register.
are explained below.
The current task/process (CTP) field is updated by the operating system software to provide task/process
ID information. The OTR register can only be accessed by supervisor data attributes. Only CPU writes to
this register will be transmitted. This register is not accessible via the auxiliary port download request
message.
24-8
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•
•
•
•
•
•
•
•
Ownership trace register
Device ID register
Development control register
Mode control register 4-bit
User base address register
Read/write access register
Upload/download information register
Data trace attributes register 1
Data trace attributes register 2
Programming Model
Register Map
User-Mapped Register (OTR)
This is the only READI register that is reset by HRESET.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 24-4
http://www.nexus5001.org/
NOTE
shows the location of the register bits. Their functions
.
Freescale Semiconductor