MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 964

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Development Support
Note: LCTRL2 is cleared following reset.
For each watchpoint, three control register fields (LWxIA, LWxLA, LWxLD) must be programmed. For
a watchpoint to be asserted, all three conditions must be detected.
23-50
14:15
17:18
21:27
Bits
16
19
20
28
29
30
31
BRKNOMSK
LW1LADC
LW1LDDC
DLW0EN
DLW1EN
SLW0EN
SLW1EN
LW1LA
LW1LD
Name
—
Table 23-25. LCTRL2 Bit Descriptions (continued)
2nd L-bus watchpoint
L-addr events selection
00 match from comparator E
01 match from comparator F
10 match from comparators (E&F)
11 match from comparators (E | F)
2nd L-bus watchpoint
care/don’t care L-addr events
0 Don’t care
1 Care
2nd L-bus watchpoint
L-data events selection
00 match from comparator G
01 match from comparator H
10 match from comparators (G&H)
11 match from comparator (G | H)
2nd L-bus watchpoint
care/don’t care L-data events
0 Don’t care
1 Care
Internal breakpoints non-mask bit
0 masked mode; breakpoints are recognized only when MSR[RI]=1 (reset value)
1 non-masked mode; breakpoints are always recognized
Reserved
Development port trap enable selection of the 1st L-bus watchpoint
(read only bit)
0 trap disabled (reset value)
1 trap enabled
Development port trap enable selection of the 2nd L-bus watchpoint
(read only bit)
0 trap disabled (reset value)
1 trap enabled
Software trap enable selection of the 1st L-bus watchpoint
0 trap disabled (reset value)
1 trap enabled
Software trap enable selection of the 2nd L-bus watchpoint
0 trap disabled (reset value)
1 trap enabled
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Freescale Semiconductor