MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 851

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

19.4.12 TPU Module Configuration Register 3 (TPUMCR3)
Freescale Semiconductor
SRESET
11:15
Bits
0:6
10
7
8
9
Field
Addr
101
110
111
EPSCK
PWOD
TCR2PSCK
2
EPSCKE
—
MSB
0
Name
Table 19-20. System Clock Frequency/Minimum Guaranteed Detected Pulse
—
1
Figure 19-22. TPUMCR3 — TPU Module Configuration Register 3
2
Reserved
Prescaler write-once disable bit. The PWOD bit does not lock the EPSCK field and the EPSCKE
bit.
0 Prescaler fields in MCR are write-once
1 Prescaler fields in MCR can be written anytime
TCR2 prescaler 2
0 Prescaler clock source is divided by one.
1 Prescaler clock is divided. See divider definitions in
Enhanced pre-scaler enable
0 Disable enhanced prescaler (use standard prescaler)
1 Enable enhanced prescaler. System clock will be divided by the value in EPSCK field.
Reserved
Enhanced prescaler value that will be loaded into the enhanced prescaler counter. Prescaler
value(EPSCK + 1) x 2. Refer to
—
3
128
256
512
4
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 19-21. TPUMCR3 Bit Descriptions
5
6
0x30 402A (TPU_A), 0x30 442A (TPU_B)
PWOD
12.8 µs
25.6 µs
6.4 µs
7
0000_0000_0000_0000
TCR2PSCK2 EPSCKE
Section 19.3.8, “Prescaler Control for
8
15.51 µs
Description
3.88 µs
7.76 µs
9
Table
—
10
19-5.
12.80 µs
3.20 µs
6.40 µs
11
TCR1,” for details.
12
EPSCK
Time Processor Unit 3
13
2.29 µs
4.57 µs
9.14 µs
14
LSB
15
19-21