EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 474

IC ARM9 SOC ENH UNIV 352PBGA

EP9315-CBZ

Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-CBZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1139

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11
11-34
Universal Serial Bus Host Controller
EP93xx User’s Guide
POCI:
PRS:
PPS:
Copyright 2007 Cirrus Logic
(READ) PortOverCurrentIndicator. This bit is only valid
when the Root Hub is configured in such a way that
overcurrent conditions are reported on a per-port basis. If
per-port overcurrent reporting is not supported, this bit is
set to 0. If cleared, all power operations are normal for this
port. If set, an overcurrent condition exists on this port.
This bit always reflects the overcurrent input signal
0 = no overcurrent condition.
1 = overcurrent condition detected.
(WRITE) ClearSuspendStatus. The HCD writes a “1” to
initiate a resume. Writing a “0” has no effect. A resume is
initiated only if PortSuspendStatus is set.
(READ) PortResetStatus. When this bit is set by a write to
SetPortReset, port reset signaling is asserted. When reset
is completed, this bit is cleared when
PortResetStatusChange is set. This bit cannot be set if
CurrentConnectStatus is cleared.
0 = port reset signal is not active
1 = port reset signal is active
(WRITE) SetPortReset. The HCD sets the port reset
signaling by writing a “1” to this bit. Writing a “0” has no
effect. If CurrentConnectStatus is cleared, this write does
not set PortResetStatus, but instead sets
ConnectStatusChange. This informs the driver that it
attempted to reset a disconnected port.
(READ) PortPowerStatus. This bit reflects the port’s power
status, regardless of the type of power switching
implemented. This bit is cleared if an overcurrent condition
is detected. HCD sets this bit by writing SetPortPower or
SetGlobalPower. HCD clears this bit by writing
ClearPortPower or ClearGlobalPower. Which power
control switches are enabled is determined by
PowerSwitchingMode and PortPortControlMask[NDP].
In global switching mode (PowerSwitchingMode=0), only
Set/ClearGlobalPower controls this bit. In per-port power
switching (PowerSwitchingMode=1), if the
PortPowerControlMask[NDP] bit for the port is set, only
Set/ClearPortPower commands are enabled. If the mask
is not set, only Set/ClearGlobalPower commands are
enabled. When port power is disabled,
CurrentConnectStatus, PortEnableStatus,
PortSuspendStatus, and PortResetStatus should be reset.
0 = port power is off
1 = port power is on
DS785UM1

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