EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 569

IC ARM9 SOC ENH UNIV 352PBGA

EP9315-CBZ

Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-CBZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1139

Available stocks

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Part Number
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Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9315-CBZ
Manufacturer:
ALTERA
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Part Number:
EP9315-CBZ
Manufacturer:
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Quantity:
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48
UART2LinCtrlLow
DS785UM1
31
15
Definition:
Bit Descriptions:
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
UART Line Control Register Middle.
RSVD:
BR:
0x808D_0010 - Read/Write
0x0000_0000
UART Line Control Register Low.
RSVD:
BR:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Baud Rate Divisor bits [15:8]. Most significant byte of baud
rate divisor. These bits are cleared to 0 on reset.
Reserved. Unknown During Read.
Baud Rate Divisor bits [7:0]. Least significant byte of baud
rate divisor. These bits are cleared to 0 on reset. The baud
rate divisor is calculated as follows:
Baud rate divisor BAUDDIV = (F
rate)) –1
where F
baud rate divisor of zero is not allowed and will result in no
data transfer.
24
8
RSVD
UARTCLK
23
7
is the UART reference clock frequency. A
22
6
21
5
20
4
UARTCLK
BR
19
3
EP93xx User’s Guide
/ (16 * Baud
18
2
17
1
UART2
15-11
16
0
15

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