EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 539

IC ARM9 SOC ENH UNIV 352PBGA

EP9315-CBZ

Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9315-CBZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1139

Available stocks

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Price
Part Number:
EP9315-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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EP9315-CBZ
Manufacturer:
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Part Number:
EP9315-CBZ
Manufacturer:
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14.1 Registers
UART Register Descriptions
UART1Data
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
For words to be transmitted:
30
14
• • if the FIFOs are enabled, data written to this location is pushed onto the transmit
29
13
FIFO
• if the FIFOs are not enabled, data is stored in the transmitter holding register (the
bottom word of the transmit FIFO). The write operation initiates transmission from
the UART. The data is prefixed with a start bit, appended with the appropriate parity
bit (if parity is enabled), and a stop bit. The resultant word is then transmitted.
For received words:
• if the FIFOs are enabled, the data byte is extracted, and a 3-bit status (break, frame
and parity) is pushed onto the 11-bit wide receive FIFO
• if the FIFOs are not enabled, the data byte and status are stored in the receiving
holding register (the bottom word of the receive FIFO).
The received data byte is read by performing reads from the UART1Data register
while the corresponding status information can be read by a successive read of the
UART1RXSts register.
28
12
0x808C_0000 - Read/Write
0x0000_0000
UART Data Register
RSVD:
DATA:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
UART Data: read for receive data, write for transmit data
24
8
RSVD
23
7
UART1 With HDLC and Modem Control Signals
22
6
21
5
20
4
DATA
19
3
EP93xx User’s Guide
18
2
17
1
14-17
16
0
14

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