EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 489

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

DS785UM1
Bit Descriptions:
RSVD:
IDCY:
WST1:
RBLE:
WST2:
Copyright 2007 Cirrus Logic
• A single Read or Write access, or
• The first Read or Write access of a burst-of-four
Reserved - Unknown During Read
Idle Cycle - Read/Write
The value written to this field specifies the memory data
bus turnaround time between a Read access and a Write
access. The turnaround time is specified by (IDCY + 1)
HCLKs. For example, if IDCY = 0xA, the turnaround time
is 10 + 1 = 11 cycles of HCLK.
Wait States1 - Read/Write
The value written to this field specifies the ‘number of
HCLK cycles, minus 1’ that are inserted as wait cycles into
the timing for:
The number of wait cycles is specified by (WST1 + 1)
HCLKs. For example, if WST1 = 0x3, 3 + 1 = 4 cycles of
HCLK are inserted into the access timing.
On reset, this field defaults to 0x1F (slowest access) to
enable booting from ROM or FLASH memory device
types.
Read Byte Lane Enable - Read/Write
The value written to this bit specifies the output values on
the DQMn[3:0] pins during a Read access:
0 - DQMn[3:0] pins are all driven HIGH during memory
Reads (default at reset for bank 1-3,6,7)
1 - DQMn[3:0] pins are all driven LOW during memory
Reads (default at reset for bank 0)
For memory Writes, this bit must written to ‘1’.
Wait States2 - Read/Write
The value in this field specifies the ‘number of HCLK
cycles, minus 1’ that are inserted as wait cycles into the
timing for each of the 2nd, 3rd, and 4th accesses of Read
or Write burst-of-four accesses.
accesses.
Static Memory Controller
EP93xx User’s Guide
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