EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 675

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

I
I2SRX0Lft
DS785UM1
2
21.7.2 I
S RX Register Descriptions
31
15
Definition:
Bit Descriptions:
Address:
Default:
The following table summarizes the register set in the I
registers listed are addressable. The left and right data registers for channels 0, 1 and 2 can
be accessed by both APB and DMA accesses. The remaining registers are concerned with
control/status information and can be only accessed through the APB bus.
30
14
2
0x8082_004C
0x8082_005C
0x8082_006C
0x8082_0040
0x8082_0044
0x8082_0048
0x8082_0050
0x8082_0054
0x8082_0058
0x8082_0060
0x8082_0064
0x8082_0068
S RX Registers
Address
29
13
28
12
TX2 Channel Enable
RSVD:
i2s_tx2_EN:
0x8082_0040 - Read Only
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
27
11
Width
32
32
32
32
32
32
26
10
2
2
2
1
1
1
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
TX2 Channel Enable
Reset
Value
Table 21-8. I
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
24
i2s_rx0_left
i2s_rx0_left
8
I2SRXLinCtrlData
I2SRXWrdLen
2
23
7
I2SRX0En
I2SRX1En
I2SRX2En
S RX Registers
I2SRX0Lft
I2SRX0Rt
I2SRX1Lft
I2SRX1Rt
I2SRX2Lft
I2SRX2Rt
I2SRXCtrl
Name
22
6
2
S Receiver block. Each of the
21
5
Left Receive data register for channel 0
Right Receive data register for channel 0
Left Receive data register for channel 1
Right Receive data register for channel 1
Left Receive data register for channel 2
Right Receive data register for channel 2
Line Control data register
Control register
Word Length
RX0 Channel Enable
RX1 Channel Enable
RX2 Channel Enable
20
4
Description
19
3
EP93xx User’s Guide
18
2
I
2
S Controller
17
1
21-19
16
0
21