ST72F324J4B5 STMicroelectronics, ST72F324J4B5 Datasheet - Page 16

• Manufacturer Part Number: ST72F324J4B5
• Description: MCU 8BIT 16K FLASH 5V 42DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J4B5

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 10 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4848

ST72324Jx ST72324Kx
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
2. The bits associated with unavailable pins must always keep their reset value.
3. The Timer A Input Capture 2 pin is not available (not bonded).
4. The Timer A Output Compare 2 pin is not available (not bonded).
Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in Flash de-
vices but are present in the emulator. For compatibility with the emulator, it is recommended to perform a
dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.
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1
– In Flash devices:
– The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values.
tion, the values of the I/O pins are returned instead of the DR register contents.
The TAIC2HR and TAIC2LR registers are not present. Bit 5 of the TACSR register (ICF2) is forced
by hardware to 0. Consequently, the corresponding interrupt cannot be used.
Bit 4 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding in-
terrupt cannot be used.