ST72F324J4B5 STMicroelectronics, ST72F324J4B5 Datasheet - Page 66

• Manufacturer Part Number: ST72F324J4B5
• Description: MCU 8BIT 16K FLASH 5V 42DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J4B5

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 10 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4848

ST72324Jx ST72324Kx
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
2. If the OCiE bit is not set, the OCMPi pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 41. Output Compare Block Diagram
66/164
1
16-bit
ister, the output compare function is inhibited
until the OCiLR register is also written.
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMPi are set while the counter value equals
the OCiR register value (see
67). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
CIRCUIT
OC2R Register
COUNTER
16-bit
Figure 43 on page
CPU
i
R register and the
CPU
Figure 42 on page
/4, f
/2, OCFi and
OC1E
CPU
OCIE
OC2E
OCF1
/8 or in
67).
FOLV2 FOLV1
6. In Flash devices, the TAOC2HR, TAOC2LR
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
registers are “write only” in Timer A. The corre-
sponding event cannot be generated (OCF2 is
forced by hardware to 0).
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
Latch
Latch
1
2
OCMP1
OCMP2
Pin
Pin