ST72F324J4B5 STMicroelectronics, ST72F324J4B5 Datasheet - Page 160

• Manufacturer Part Number: ST72F324J4B5
• Description: MCU 8BIT 16K FLASH 5V 42DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324J4B5

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 10 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4848

ST72324Jx ST72324Kx
KNOWN LIMITATIONS (Cont’d)
To avoid this, a semaphore is set to '1' before
checking the level change. The semaphore is
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore
status is checked and if it is '1' this means that the
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction.
There is another possible case, that is, if writing to
PxOR or PxDDR is done with global interrupts dis-
abled (interrupt mask bit set). In this case, the
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is
done after the global interrupts are enabled (inter-
rupt mask bit reset) and by checking the status of
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in-
voked with the call instruction.
To implement the workaround, the following soft-
ware sequence is to be followed for writing into the
PxOR/PxDDR registers. The example is for Port
PF1 with falling edge interrupt sensitivity. The soft-
ware sequence is given for both cases (global in-
terrupt disabled/enabled).
Case 1: Writing to PxOR or PxDDR with Global In-
terrupts Enabled:
LD A,#01
LD sema,A
LD A,PFDR
AND A,#02
LD X,A
PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
LD PFOR,A
LD A,PFDR
AND A,#02
LD Y,A
PxOR/PxDDR
LD A,X
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema
edge is detected
CP A,#01
160/164
1
; set the semaphore to '1'
; store the level before writing to
; store the level after writing to
; check for falling edge
; check the semaphore status if
; Write to PFOR
jrne OUT
call call_routine; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
SIM
LD A,PFDR
AND A,#$02
LD X,A
PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write into PFDDR
LD A,#$ff
LD PFOR,A
LD A,PFDR
AND A,#$02
LD Y,A
PxOR/PxDDR
LD A,X
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A
detected
RIM
LD A,sema
CP A,#$01
jrne OUT
call call_routine; call the interrupt routine
RIM
OUT:
; entry to call_routine
; entry to interrupt routine
; set the interrupt mask
; store the level before writing to
; store the level after writing to
; check for falling edge
; set the semaphore to '1' if edge is
; check the semaphore status
RIM
; reset the interrupt mask
; Write to PFOR