MC908LJ24CPBE Freescale Semiconductor, MC908LJ24CPBE Datasheet - Page 425

• Manufacturer Part Number: MC908LJ24CPBE
• Description: IC MCU 24K FLASH 8MHZ SPI 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.4.4 LVI Trip Selection
22.5 LVI Status Register
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
NOTE:
Address:
Reset:
The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select
whether the LVI is configured for 5V or 3 V operation. (See
Configuration Registers
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V
Section 24. Electrical Specifications
The LVI status register (LVISR) controls LVI interrupt functions and
indicates if the V
LVIOUT — LVI Output Bit
Read: LVIOUT
Write:
This read-only flag becomes set when the V
V
TRIPF
$FE0F
Bit 7
TRIPF
0
trip voltage (see
[5V] or V
Table 22-1. LVI Status Register (LVISR)
Low-Voltage Inhibit (LVI)
= Unimplemented
V
LVIIE
TRIPF
DD
6
0
Table 22-2. LVIOUT Bit Indication
V
V
voltage was detected below the V
DD
DD
< V
TRIPF
V
> V
< V
LVIIF
DD
DD
5
0
TRIPR
TRIPF
(CONFIG).)
< V
Table
[3V]) may be lower than this. (See
TRIPR
LVIIACK
22-2). Reset clears the LVIOUT bit.
4
0
0
for the actual trip point voltages.)
Previous value
3
0
0
LVIOUT
DD
0
1
voltage falls below the
2
0
0
Low-Voltage Inhibit (LVI)
TRIPF
LVI Status Register
1
0
0
Section 5.
level.
Data Sheet
Bit 0
0
0
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