PIC18F87J11-I/PT Microchip Technology, PIC18F87J11-I/PT Datasheet
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... Microchip Technology Inc. PIC18F87J11 Family 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology Data Sheet DS39778D ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F87J11 128 kB 3930 © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Peripheral Highlights (continued): • 8-Bit Parallel Master Port/Enhanced Parallel Slave Port (PMP/EPSP) with 16 Address Lines • Dual Analog Comparators with Input Multiplexing • 10-Bit 15-Channel Analog-to-Digital Converter module (A/D): ...
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... PIC18F87J11 FAMILY Pin Diagrams 64-Pin TQFP RE1/PMWR/P2C 1 RE0/PMRD/P2D 2 RG0/PMA8/ECCP3/P3A 3 RG1/PMA7/TX2/CK2 4 RG2/PMA6/RX2/DT2 5 RG3/PMCS1/CCP4/P3D 6 MCLR 7 RG4/PMCS2/CCP5/P1D DDCORE CAP RF7/SS1 11 RF6/AN11/C1INA 12 RF5/AN10/C1INB/CV 13 REF RF4/AN9/C2INA 14 RF3/AN8/C2INB 15 RF2/PMA5/AN7/C1OUT 16 Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting. DS39778D-page PIC18F6XJ11 PIC18F6XJ16 RB0/INT0/FLT0 48 RB1/INT1/PMA4 47 46 RB2/INT2/PMA3 ...
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... The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings. 2: P1B, P1C, P3B, and P3C pin placement depends on the ECCPMX Configuration bit setting. 3: PMP pin placement depends on the PMPMX Configuration bit setting. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY ...
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... PIC18F87J11 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Oscillator Configurations ............................................................................................................................................................ 33 3.0 Power-Managed Modes ............................................................................................................................................................. 43 4.0 Reset .......................................................................................................................................................................................... 51 5.0 Memory Organization ................................................................................................................................................................. 63 6.0 Flash Program Memory .............................................................................................................................................................. 89 7.0 External Memory Bus ................................................................................................................................................................. 99 8 Hardware Multiplier.......................................................................................................................................................... 111 9.0 Interrupts .................................................................................................................................................................................. 113 10.0 I/O Ports ................................................................................................................................................................................... 129 11.0 Parallel Master Port .................................................................................................................................................................. 153 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY DS39778D-page 7 ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 8 © 2009 Microchip Technology Inc. ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F87J11 Family offer four different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes, using crystals or ceramic resonators. ...
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... Section 27.0 “Electrical Characteristics” for time-out periods. DS39778D-page 10 1.3 Details on Individual Family Members Devices in the PIC18F87J11 Family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in three ways: 1. ...
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... I/O Ports Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY PIC18F66J11 PIC18F66J16 DC – 48 MHz DC – 48 MHz 64K 96K 32768 49152 3930 3930 ...
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... PIC18F87J11 FAMILY FIGURE 1-1: PIC18F6XJ1X (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (96 Kbytes) Data Latch 8 Instruction Bus <16> Timing Generation OSC2/CLKO OSC1/CLKI 8 MHz INTOSC INTRC Oscillator Precision Band Gap Reference ENVREG Voltage Regulator V /V DDCORE CAP ...
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... PMP ECCP1 ECCP2 ECCP3 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Data Latch 8 8 Data Memory (2.0, 3.9 Kbytes) PCLATU PCLATH Address Latch ...
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... PIC18F87J11 FAMILY TABLE 1-3: PIC18F6XJ1X PINOUT I/O DESCRIPTIONS Pin Number Pin Name 64-TQFP MCLR 7 OSC1/CLKI/RA7 39 OSC1 CLKI RA7 OSC2/CLKO/RA6 40 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. ...
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... Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. ...
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... PIC18F87J11 FAMILY TABLE 1-3: PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-TQFP RB0/FLT0/INT0 48 RB0 FLT0 INT0 RB1/INT1/PMA4 47 RB1 INT1 PMA4 RB2/INT2/PMA3 46 RB2 INT2 PMA3 RB3/INT3/PMA2 45 RB3 INT3 PMA2 RB4/KBI0/PMA1 44 RB4 KBI0 PMA1 RB5/KBI1/PMA0 43 RB5 KBI1 PMA0 RB6/KBI2/PGC 42 RB6 KBI2 ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — ...
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... PIC18F87J11 FAMILY TABLE 1-3: PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-TQFP RD0/PMD0 58 RD0 PMD0 RD1/PMD1 55 RD1 PMD1 RD2/PMD2 54 RD2 PMD2 RD3/PMD3 53 RD3 PMD3 RD4/PMD4/SDO2 52 RD4 PMD4 SDO2 RD5/PMD5/SDI2/SDA2 51 RD5 PMD5 SDI2 SDA2 RD6/PMD6/SCK2/SCL2 50 RD6 PMD6 SCK2 SCL2 RD7/PMD7/SS2 ...
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... I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O. I/O — ...
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... PIC18F87J11 FAMILY TABLE 1-3: PIC18F6XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-TQFP RF1/AN6/C2OUT 17 RF1 AN6 C2OUT RF2/PMA5/AN7/C1OUT 16 RF2 PMA5 AN7 C1OUT RF3/AN8/C2INB 15 RF3 AN8 C2INB RF4/AN9/C2INA 14 RF4 AN9 C2INA RF5/AN10/C1INB/CV 13 REF RF5 AN10 C1INB CV REF RF6/AN11/C1INA 12 RF6 AN11 C1INA ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O. O — ...
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... PIC18F87J11 FAMILY TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS Pin Number Pin Name 80-TQFP MCLR 9 OSC1/CLKI/RA7 49 OSC1 CLKI RA7 OSC2/CLKO/RA6 50 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode). ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Description ...
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... PIC18F87J11 FAMILY TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RB0/FLT0/INT0 58 RB0 FLT0 INT0 RB1/INT1/PMA4 57 RB1 INT1 PMA4 RB2/INT2/PMA3 56 RB2 INT2 PMA3 RB3/INT3/PMA2/ 55 ECCP2/P2A RB3 INT3 PMA2 (1) ECCP2 (1) P2A RB4/KBI0/PMA1 54 RB4 KBI0 PMA1 RB5/KBI1/PMA0 53 RB5 KBI1 PMA0 ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Description ...
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... PIC18F87J11 FAMILY TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RD0/AD0/PMD0 72 RD0 AD0 (6) PMD0 RD1/AD1/PMD1 69 RD1 AD1 (6) PMD1 RD2/AD2/PMD2 68 RD2 AD2 (6) PMD2 RD3/AD3/PMD3 67 RD3 AD3 (6) PMD3 RD4/AD4/PMD4/SDO2 66 RD4 AD4 (6) PMD4 SDO2 RD5/AD5/PMD5/ 65 SDI2/SDA2 RD5 AD5 (6) PMD5 SDI2 ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Description ...
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... PIC18F87J11 FAMILY TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RF1/AN6/C2OUT 23 RF1 AN6 C2OUT RF2/PMA5/AN7/C1OUT 18 RF2 PMA5 AN7 C1OUT RF3/AN8/C2INB 17 RF3 AN8 C2INB RF4/AN9/C2INA 16 RF4 AN9 C2INA RF5/PMD2/AN10/ 15 C1INB/CV REF RF5 (7) PMD2 AN10 C1INB CV REF RF6/PMD1/AN11/C1INA 14 RF6 ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Description ...
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... PIC18F87J11 FAMILY TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RH0/A16 79 RH0 A16 RH1/A17 80 RH1 A17 RH2/A18/PMD7 1 RH2 A18 (7) PMD7 RH3/A19/PMD6 2 RH3 A19 (7) PMD6 RH4/PMD3/AN12/ 22 P3C/C2INC RH4 (7) PMD3 AN12 (5) P3C C2INC RH5/PMBE/AN13/ 21 P3B/C2IND RH5 (7) PMBE AN13 (5) P3B ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set. 7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Pin Buffer Description ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 32 © 2009 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F87J11 family of devices can be operated in eight different oscillator modes High-Speed Crystal/Resonator 2. HSPLL High-Speed Crystal/Resonator with Software PLL Control 3. EC External Clock with F OSC 4. ECPLL External Clock with Software PLL Control 5. INTIO1 Internal Oscillator Block with F Output on RA6 and I/O on RA7 6 ...
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... PIC18F87J11 FAMILY 2.2 Control Registers The OSCCON register (Register 2-1) controls the main aspects of the device clock’s operation. It selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators. ...
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... WDT and Fail-Safe Clock Monitor. The internal oscillator block is discussed in more detail in Section 2.5 “Internal Oscillator Block”. The PIC18F87J11 Family includes features that allow by the the device clock source to be switched from the main the ...
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... SCS1:SCS0 bits at any given time. 2.3.2 OSCILLATOR TRANSITIONS PIC18F87J11 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... AN943, “Practical PIC Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table 2-2 for additional information. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Osc Type Freq. ...
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... PIC18F87J11 FAMILY 2.4.2 EXTERNAL CLOCK INPUT (EC MODES) The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided available on the OSC2 pin ...
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... Internal Oscillator Block The PIC18F87J11 Family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcon- troller’s clock source. This may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. ...
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... DD 2.6 Reference Clock Output In addition to the F tor modes, the device clock in the PIC18F87J11 family can also be configured to provide a reference clock out- put signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock sub-multiples to drive external devices in the application ...
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... Base clock value divided by 2 0000 = Base clock value Note 1: If ROSEL = oscillator must be configured as the default oscillator with the FOSC Configuration bits to maintain clock output during Sleep mode. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 (1) ROSEL ...
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... PIC18F87J11 FAMILY 2.7 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated pri- mary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. ...
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... POWER-MANAGED MODES The PIC18F87J11 Family of devices provides the ability to manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: • ...
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... PIC18F87J11 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON< ...
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... These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2) ...
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... PIC18F87J11 FAMILY 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times ...
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... These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... PIC18F87J11 FAMILY 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 50 © 2009 Microchip Technology Inc. ...
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... RESET The PIC18F87J11 Family of devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Configuration Mismatch (CM) f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset ...
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... PIC18F87J11 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 IPEN — CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘ ...
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... To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. 4.4 Brown-out Reset (BOR) The PIC18F87J11 family of devices incorporates a simple Brown-out Reset function when the internal reg- ulator is enabled (ENVREG pin is tied to V drop of V below V ...
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... Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F87J11 Family devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μ ms. ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY T PWRT , V RISE > 3. PWRT ): CASE PWRT DS39778D-page 55 ...
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... PIC18F87J11 FAMILY 4.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
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... PIC18F87J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F6XJ1X PIC18F8XJ1X POSTINC2 PIC18F6XJ1X PIC18F8XJ1X POSTDEC2 PIC18F6XJ1X PIC18F8XJ1X PREINC2 PIC18F6XJ1X PIC18F8XJ1X PLUSW2 PIC18F6XJ1X PIC18F8XJ1X FSR2H PIC18F6XJ1X PIC18F8XJ1X FSR2L PIC18F6XJ1X PIC18F8XJ1X STATUS PIC18F6XJ1X PIC18F8XJ1X TMR0H PIC18F6XJ1X PIC18F8XJ1X TMR0L ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
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... PIC18F87J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR3 PIC18F6XJ1X PIC18F8XJ1X PIR3 PIC18F6XJ1X PIC18F8XJ1X PIE3 PIC18F6XJ1X PIC18F8XJ1X IPR2 PIC18F6XJ1X PIC18F8XJ1X PIR2 PIC18F6XJ1X PIC18F8XJ1X PIE2 PIC18F6XJ1X PIC18F8XJ1X IPR1 PIC18F6XJ1X PIC18F8XJ1X PIR1 PIC18F6XJ1X PIC18F8XJ1X PIE1 PIC18F6XJ1X PIC18F8XJ1X RCSTA2 ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY MCLR Resets, WDT Reset, Power-on Reset, RESET Instruction, Brown-out Reset Stack Resets, ...
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... PIC18F87J11 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PMADDRH PIC18F6XJ1X PIC18F8XJ1X PMDOUT1H PIC18F6XJ1X PIC18F8XJ1X PMADDRL PIC18F6XJ1X PIC18F8XJ1X PMDOUT1L PIC18F6XJ1X PIC18F8XJ1X PMDIN1H PIC18F6XJ1X PIC18F8XJ1X PMDIN1L PIC18F6XJ1X PIC18F8XJ1X PMCONH PIC18F6XJ1X PIC18F8XJ1X PMCONL PIC18F6XJ1X PIC18F8XJ1X PMMODEH PIC18F6XJ1X PIC18F8XJ1X PMMODEL ...
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... NOP instruction). The entire PIC18F87J11 Family of devices offers three different on-chip Flash program memory sizes, from 64 Kbytes (up to 16,384 single-word instructions) to 128 Kbytes (65,536 single-word instructions). The program memory maps for individual family members are shown in Figure 5-3 ...
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... Configuration Words, CONFIG1 through CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices in the PIC18F87J11 Family are shown in Table 5-1. Their location in the memory map is shown with the other memory vectors in Figure 5-2. Additional details on the device Configuration Words are provided in Section 24.1 “ ...
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... Unimplemented: Read as ‘0’ Note 1: Implemented only on 80-pin devices. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory; above this, the device accesses external program memory up to the 2-Mbyte program space limit ...
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... In practical terms, this means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 5-3: MEMORY MAPS FOR PIC18F87J11 FAMILY PROGRAM MEMORY MODES (1) Microcontroller Mode Extended Microcontroller Mode On-Chip ...
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... Microchip Technology Inc. PIC18F87J11 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... PIC18F87J11 FAMILY 5.1.6.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... PIC18F87J11 FAMILY 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruc- tion Register (IR) during Q4 ...
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... ADDWF © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... The memory space is divided into as many as 16 banks that contain 256 bytes each. The PIC18F87J11 family implements all available banks and provide 3936 bytes of data memory available to the user. Figure 5-7 shows the data memory organization for the devices ...
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... FIGURE 5-7: DATA MEMORY MAP FOR PIC18F87J11 FAMILY DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
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... PIC18F87J11 FAMILY FIGURE 5-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
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... Resets and interrupts) and those related to the peripheral functions. The Reset and interrupt registers are described in their respective chapters, while the TABLE 5-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J11 FAMILY DEVICES Address Name Address Name ...
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... Since the bit remains in a given state until changed, users should always verify the state of ADSHR before writing to any of the shared SFR addresses. TABLE 5-4: SHARED SFR ADDRESSES FOR PIC18F87J11 FAMILY DEVICES Address Name FD3h (D) OSCCON ...
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... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) File Name Bit 7 Bit 6 Bit 5 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F87J11 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 FSR2H — — FSR2L Indirect Data Memory Address Pointer 2 Low Byte STATUS — — TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON ...
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... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 ECCP1DEL P1RSEN P1DC6 P1DC5 CCPR1H Capture/Compare/PWM Register 1 HIgh Byte CCPR1L Capture/Compare/PWM Register 1 Low Byte CCP1CON P1M1 P1M0 DC1B1 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 ...
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... PIC18F87J11 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 (7) TRISJ TRISJ7 TRISJ6 TRISJ5 (7) TRISH TRISH7 TRISH6 TRISH5 TRISG — — TRISF TRISF7 TRISF6 TRISF5 TRISE TRISE7 TRISE6 TRISE5 TRISD TRISD7 TRISD6 TRISD5 TRISC TRISC7 ...
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... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 CCPR4H Capture/Compare/PWM Register 4 High Byte CCPR4L Capture/Compare/PWM Register 4 Low Byte CCP4CON — — DC4B1 CCPR5H Capture/Compare/PWM Register 5 High Byte CCPR5L Capture/Compare/PWM Register 5 Low Byte CCP5CON — — DC5B1 ...
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... PIC18F87J11 FAMILY 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-4, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC bits, then the write to these five bits is disabled ...
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... Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 “General © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Purpose Register File”), or a location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. ...
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... PIC18F87J11 FAMILY 5.4.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
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... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For exam- ple, using an FSR to point to one of the virtual registers will not result in successful operations ...
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... PIC18F87J11 FAMILY 5.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 5.2.4 “ ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 000h 060h Bank 0 100h Bank 1 through Bank 14 F00h ...
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... PIC18F87J11 FAMILY 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
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... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F87J11 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC18F87J11 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
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... MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F87J11 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
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... Note 1: Unlike previous PIC18 Flash devices, members of the PIC18F87J11 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence ...
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... PIC18F87J11 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF ...
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... FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PROGRAMMING). The PIC18F87J11 Family of devices have a feature that allows programming a single word (two bytes). This feature is enable when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1 ...
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... PIC18F87J11 FAMILY 6.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.4 UNEXPECTED TERMINATION OF ...
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... The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8 and 16-Bit Data Width modes and three address widths bits. TABLE 7-1: PIC18F87J11 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS Name Port RD0/AD0 PORTD RD1/AD1 ...
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... PIC18F87J11 FAMILY 7.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 7-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions ...
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... Address and Data Width The PIC18F87J11 Family of devices can be indepen- dently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software ...
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... Program Memory Modes and the External Memory Bus The PIC18F87J11 Family of devices is capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the EBDIS bit ...
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... BYTE WRITE MODE Figure 7-1 shows an example of 16-Bit Byte Write mode for PIC18F87J11 Family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories ...
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... WORD WRITE MODE Figure 7-2 shows an example of 16-Bit Word Write mode for PIC18F87J11 Family devices. This mode is used for word-wide memories which include some of the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
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... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
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... PIC18F87J11 FAMILY 7.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 and Figure 7-5. FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
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... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
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... PIC18F87J11 FAMILY 7.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-7 and Figure 7-8. FIGURE 7-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
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... Microchip Technology Inc. PIC18F87J11 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 110 © 2009 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8-2: ...
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... PIC18F87J11 FAMILY Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = 16 (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • 2 (ARG1L • ...
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... INTERRUPTS Members of the PIC18F87J11 Family of devices have multiple interrupt sources and an interrupt priority fea- ture that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
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... PIC18F87J11 FAMILY FIGURE 9-1: PIC18F87J11 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:5, 3:0> PIE2<7:5, 3:0> IPR2<7:5, 3:0> PIR3<7, 0> PIE3<7, 0> IPR3<7, 0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:5, 3:0> PIE2<7:5, 3:0> IPR2<7:5, 3:0> PIR3<7, 0> PIE3<7, 0> ...
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... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... PIC18F87J11 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 ...
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... PIC18F87J11 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY U-0 R/W-0 R/W-0 — BCL1IF LVDIF U = Unimplemented bit, read as ‘0’ ...
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... PIC18F87J11 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 SSP2IF BCL2IF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IF: MSSP2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software Waiting to transmit/receive ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...
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... PIC18F87J11 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit ...
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... Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 ...
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... PIC18F87J11 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY U-0 R/W-1 R/W-1 — BCL1IP LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F87J11 FAMILY REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IP: MSSP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
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... PIC18F87J11 FAMILY 9.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
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... RD TRIS PORT © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
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... PIC18F87J11 FAMILY Table 10-2 summarizes the output capabilities of the ports. Refer to the “Absolute Maximum Ratings” in Section 27.0 “Electrical Characteristics” for more details. TABLE 10-2: OUTPUT DRIVE LEVELS Port Drive Description PORTA Minimum Intended for indication. PORTF PORTG (1) PORTH PORTD ...
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... Bit is set bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits 1 = Open-drain output on SDOx pin enabled 0 = Open-drain output disabled © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 R/W-0 CCP5OD CCP4OD ECCP3OD U = Unimplemented bit, read as ‘0’ ...
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... PIC18F87J11 FAMILY REGISTER 10-4: PADCFG1: I/O PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-1 Unimplemented: Read as ‘0’ bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit ...
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... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate PMP configuration when the PMPMX Configuration bit is ‘0’; available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O Type ...
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... PIC18F87J11 FAMILY TABLE 10-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 (1) (1) PORTA RA7 RA6 (1) (1) LATA LATA7 LATA6 (1) (1) TRISA TRISA7 TRISA6 (2) ANCON0 PCFG7 PCFG6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: Implemented only in specific oscillator modes (FOSC2 Configuration bit = 0); otherwise read as ‘0’. ...
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... Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin devices only). Default assignment is RC1. 2: All other pin functions are disabled when ICSP™ or ICD is enabled. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O Type O DIG LATB< ...
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... PIC18F87J11 FAMILY TABLE 10-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB7 LATB6 TRISB TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O Description Type DIG LATC< ...
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... PIC18F87J11 FAMILY TABLE 10-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC7 LATBC6 TRISC TRISC7 TRISC6 10.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. All pins on PORTD are digital only and tolerate voltages ...
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... Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PMP I/O. 2: Available on 80-pin devices only. 3: Default configuration for PMP (PMPMX Configuration bit = 1). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O Type O DIG LATD<0> data output PORTD< ...
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... PIC18F87J11 FAMILY TABLE 10-10: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RD6/AD6/ RD6 0 PMD6/SCK2/ 1 SCL2 (2) AD6 x x (3) PMD6 x x SCK2 0 1 SCL2 0 1 RD7/AD7/ RD7 0 PMD7/SS2 1 (2) AD7 x x (3) PMD7 x x SS2 x Legend Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’ ...
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... The pull-ups are disabled on any device Reset. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY PORTE is also multiplexed with Enhanced PWM outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For all devices, their default assignments are on PORTE< ...
Page 142
... PIC18F87J11 FAMILY TABLE 10-12: PORTE FUNCTIONS TRIS Pin Name Function Setting RE0/AD8/ RE0 0 PMRD/P2D 1 (3) AD8 x x (5) PMRD x x P2D 0 RE1/AD9/ RE1 0 PMWR/P2C 1 (3) AD9 x x (5) PMWR x x P2C 0 RE2/AD10/ RE2 0 PMBE/P2B 1 (3) AD10 x x (5) PMBE x P2B 0 RE3/AD11/ RE3 0 PMA13/P3C/ 1 REFO ...
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... LATE7 LATE6 TRISE TRISE7 TRISE6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O Type O DIG LATE<5> data output PORTE<5> data input. O DIG External memory interface, address/data bit 13 output. ...
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... PIC18F87J11 FAMILY 10.7 PORTF, LATF and TRISF Registers PORTF is a 7-bit wide, bidirectional port. Only pin 7 of PORTF has no analog input the only pin that can tolerate voltages up to 5.5V. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output ...
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... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O I/O Type ...
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... PIC18F87J11 FAMILY TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 PORTF RF7 RF6 LATF LATF7 LATF6 TRISF TRISF7 TRISF6 TRISF5 (1) ANCON0 PCFG7 PCFG6 (1) ANCON1 PCFG15 PCFG14 PCFG13 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. ...
Page 147
... Legend Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O Type DIG LATG<0> data output. ...
Page 148
... PIC18F87J11 FAMILY TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 PORTG RDPU REPU LATG — — TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on 64-pin devices, read as ‘0’. 10.9 ...
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... Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments are PORTE<6:3>. 2: Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY I/O Description Type DIG LATH<0> data output. ...
Page 150
... PIC18F87J11 FAMILY TABLE 10-18: PORTH FUNCTIONS (CONTINUED) TRIS Pin Name Function I/O Setting RH7/PMWR/ RH7 O 0 AN15/P1B I 1 (2) PMWR AN15 I (1) P1B O 0 Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). ...
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... EBDIS control bit (MEMCON<7>). The TRISJ bits are also overridden. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Each of the PORTJ pins has a weak internal pull-up. A single control bit can turn off all the pull-ups. This is performed by clearing bit RJPU (PORTG<5>). The weak pull-up is automatically turned off when the port pin is configured as an output ...
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... PIC18F87J11 FAMILY TABLE 10-20: PORTJ FUNCTIONS TRIS Pin Name Function Setting RJ0/ALE RJ0 0 1 ALE x RJ1/OE RJ1 RJ2/WRL RJ2 0 1 WRL x RJ3/WRH RJ3 0 1 WRH x RJ4/BA0 RJ4 0 1 BA0 x RJ5/CE RJ5 RJ6/LB RJ6 RJ7/UB RJ7 Legend Output Input, DIG = Digital Output Schmitt Buffer Input Don’ ...
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... FIGURE 11-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Key features of the PMP module include: • Programmable Address Lines • Two Chip Select Lines • Programmable Strobe Options - Individual Read and Write Strobes or; ...
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... PIC18F87J11 FAMILY 11.1 Module Registers The PMP module has a total of 14 Special Function Registers for its operation, plus one additional register to set configuration options. Of these, 8 registers are used for control and 6 are used for PMP data transfer. 11.1.1 CONTROL REGISTERS The eight PMP Control registers are: • ...
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... Read strobe active-high (PMRD Read strobe active-low (PMRD) For Master mode 1 (PMMODEH<1:0> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY (1) (1) (1) R/W-0 R/W-0 CS2P CS1P U = Unimplemented bit, read as ‘ ...
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... PIC18F87J11 FAMILY REGISTER 11-3: PMMODEH: PARALLEL PORT MODE HIGH BYTE REGISTER R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 BUSY: Busy bit (Master mode only Port is busy 0 = Port is not busy ...
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... PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O bit 5-0 PTEN13:PTEN8: PMP Address Port Enable bits 1 = PMA<13:8> function as PMP address lines 0 = PMA<13:8> function as port I/O © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ...
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... PIC18F87J11 FAMILY REGISTER 11-6: PMEL: PARALLEL PORT ENABLE LOW BYTE REGISTER R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 PTEN7:PTEN2: PMP Address Port Enable bits 1 = PMA<7:2> function as PMP address lines 0 = PMA< ...
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... Unimplemented: Read as ‘0’ bit 3-0 OBnE: Output Buffer n Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY U-0 R-1 R-1 — OB3E OB2E U = Unimplemented bit, read as ‘ ...
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... PIC18F87J11 FAMILY 11.1.2 DATA REGISTERS The PMP module uses 6 registers for transferring data into and out of the microcontroller. They are arranged as three pairs to allow the option of 16-bit data operations: • PMDIN1H and PMDIN1L • PMDIN2H and PMDIN2L • PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L • ...
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... Master PMD<7:0> PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 11.2 Slave Port Modes The primary mode of operation for the module is con- figured using the MODE1:MODE0 bits in the PMMODEH register. The setting affects whether the module acts as a slave or a master and it determines the usage of the control pins ...
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... PIC18F87J11 FAMILY 11.2.1.1 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into the PMDIN1L register. The PMPIF and IBF flag bits are set when the write ends. The timing for the control signals in Write mode is shown in Figure 11-3 ...
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... PMRD PMWR Data Bus Control Lines © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY is generated, and the Buffer Overflow flag bit OBUF is set. If all 4 OBxE status bits are set, then the Output Buffer Empty flag (OBE) will also be set. 11.2.2.2 WRITE TO SLAVE PORT For write operations, the data is be stored sequentially, starting with Buffer 0 (PMDIN1L< ...
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... PIC18F87J11 FAMILY 11.2.3 ADDRESSABLE PARALLEL SLAVE PORT MODE In the Addressable Parallel Slave Port mode ( PMMODEH<1:0> = 01), the module is configured with two extra inputs, PMA<1:0>, which are the address lines 1 and 0. This makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers ...
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... PMA<1:0> IBF PMPIF © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY When an output buffer is read, the corresponding OBxE bit is set. The OBE flag bit is set when all the buf- fers are empty. If any buffer is already empty (OBxE = 1), the next read to that buffer will generate an OBUF event ...
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... PIC18F87J11 FAMILY 11.3 Master Port Modes In its Master modes, the PMP module provides an 8-bit data bus bits of address, and all the necessary control signals to operate a variety of external parallel devices, such as memory devices, peripherals and slave microcontrollers. To use the PMP as a master, ...
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... PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY PMA<13:0> PMD<7:0> PMCS1 PMCS2 Address Bus PMRD Data Bus ...
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... PIC18F87J11 FAMILY 11.3.5 CHIP SELECT FEATURES Up to two chip select lines, PMCS1 and PMCS2, are available for the Master modes of the PMP. The two chip select lines are multiplexed with the Most Signifi- cant bits of the address bus (PMADDRH<6> and PMADDRH<7>). When a pin is configured as a chip ...
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... READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> PMA<13:0> PMWR PMRD PMPIF BUSY FIGURE 11-13: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> Address<7:0> PMA<13:8> PMWR PMRD PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Data DS39778D-page 169 ...
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... PIC18F87J11 FAMILY FIGURE 11-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMA<13:8> PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> FIGURE 11-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS ...
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... PMCS2 PMCS1 PMD<7:0> Address<7:0> PMA<13:8> PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Data Data Address<15:8> Data ...
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... PIC18F87J11 FAMILY FIGURE 11-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 11-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-22: ...
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... PMA<13:8> PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMA<13:8> PMWR PMRD PMBE PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY LSB LSB MSB MSB DS39778D-page 173 ...
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... PIC18F87J11 FAMILY FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY FIGURE 11-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMWR PMRD ...
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... PIC18F PMD<7:0> PMALL PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 11.4.1 MULTIPLEXED MEMORY OR PERIPHERAL Figure 11-27 demonstrates the hookup of a memory or other addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address ...
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... PIC18F87J11 FAMILY 11.4.3 PARALLEL EEPROM EXAMPLE Figure 11-30 shows an example connecting parallel EEPROM to the PMP. Figure 11-31 shows a slight variation to this, configuring the connection for 16-bit data from a single EEPROM. FIGURE 11-30: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC18F PMA< ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 178 © 2009 Microchip Technology Inc. ...
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... Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
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... PIC18F87J11 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. Note 1: These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 182 © 2009 Microchip Technology Inc. ...
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... Stops Timer1 Note 1: Default (legacy) SFR at this address, available when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F87J11 FAMILY 13.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM ...
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... PIC18F87J11 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. C1 Type ( kHz 27 pF Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F87J11 FAMILY If a high-speed circuit must be located near the oscilla- tor (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 13-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. ...
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... RETURN CLRF hours RETURN © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY lowing a later Timer1 increment. This can be done by monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L reg- ister pair while the clock is low, or one-half of the period of the clock source ...
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... PIC18F87J11 FAMILY TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PMPIF ADIF PIE1 PMPIE ADIE IPR1 PMPIP ADIP (1) TMR1L Timer1 Register Low Byte (1) TMR1H Timer1 Register High Byte (1) T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module ...
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... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... PIC18F87J11 FAMILY 14.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1). It also selects the clock source options for the CCP and ECCP modules ...
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... PIC18F87J11 FAMILY 15.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS1:T3CKPS0 T3SYNC TMR3ON ECCPx Special Event Trigger ECCPx/CCPx Select from T3CON<6,3> Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. Note 1: Default (legacy) SFR at this address, available when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F87J11 FAMILY NOTES: DS39778D-page 194 © 2009 Microchip Technology Inc. ...
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... T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 16.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the ECCPx/CCPx modules. The TMR4 register is readable and writable and is cleared on any device Reset ...
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... PIC18F87J11 FAMILY 16.2 Timer4 Interrupt The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 16-1: ...
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... CAPTURE/COMPARE/PWM (CCP) MODULES Members of the PIC18F87J11 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ...
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... PIC18F87J11 FAMILY 17.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
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... Q1:Q4 CCP5CON<3:0> CCP5 pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F87J11 FAMILY 17.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... PIC18F87J11 FAMILY 17.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remains unchanged (that is, reflects the state of ...