PIC18F87J11-I/PT Microchip Technology, PIC18F87J11-I/PT Datasheet - Page 310

• Manufacturer Part Number: PIC18F87J11-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J11-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164136 - DEVELOPMENT KIT FOR PIC18AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
22.7
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.
TABLE 22-3:
DS39778D-page 310
INTCON
PIR2
PIE2
IPR2
CM1CON
CM2CON
CMSTAT
CVRCON
ANCON1
ANCON0
PORTF
LATF
TRISF
PORTH
TRISH
Legend:
Note 1:
Name
2:
(1)
(1)
Comparator Operation
During Sleep
(2)
(2)
(2)
These registers are not implemented on 64-pin devices.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
GIE/GIEH PEIE/GIEL TMR0IE
PCFG15
OSCFIE
OSCFIP
OSCFIF
CVREN
TRISF7
TRISH7
PCFG7
LATF7
Bit 7
CON
CON
RH7
RF7
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
—
PCFG14
CVROE
TRISH6
TRISF6
PCFG6
CM2IE
CM2IP
CM2IF
LATF6
Bit 6
COE
COE
RH6
RF6
—
PCFG13
TRISF5
TRISH5
CM1IE
CM1IP
CM1IF
LATF5
CVRR
CPOL
CPOL
Bit 5
RH5
RF5
—
—
EVPOL1
EVPOL1
PCFG12
TRISH4
CVRSS
TRISF4
PCFG4
INT0IE
LATF4
Bit 4
RH4
RF4
—
—
—
—
EVPOL0
EVPOL0
PCFG11
TRISH3
BCL1IE
BCL1IP
TRISF3
BCL1IF
PCFG3
LATF3
CVR3
22.8
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
RBIE
Bit 3
RH3
RF3
—
Effects of a Reset
PCFG10
TMR0IF
TRISH2
TRISF2
PCFG2
LATF2
LVDIF
LVDIE
LVDIP
CREF
CREF
CVR2
Bit 2
RH2
RF2
—
TMR3IF
TMR3IE
TMR3IP
TRISH1
TRISF1
COUT2
PCFG9
PCFG1
INT0IF
LATF1
CCH1
CCH1
CVR1
Bit 1
© 2009 Microchip Technology Inc.
RH1
RF1
CCP2IF
CCP2IE
CCP2IP
TRISH0
COUT1
PCFG8
PCFG0
CCH0
CCH0
CVR0
RBIF
Bit 0
RH0
—
—
—
on Page:
Values
Reset
58
58
57
60
60
60
58
61
59
59
61
60
60
61
60