PIC18F87J11-I/PT Microchip Technology, PIC18F87J11-I/PT Datasheet - Page 132

• Manufacturer Part Number: PIC18F87J11-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J11-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164136 - DEVELOPMENT KIT FOR PIC18AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
REGISTER 10-4:
10.2
PORTA is an 8-bit wide, bidirectional port. It may func-
tion as a 6-bit or 7-bit port, depending on the oscillator
mode selected. The corresponding Data Direction and
Output Latch registers are TRISA and LATA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin; it is also mul-
tiplexed as the Parallel Master Port data pin (in 80-pin
devices). The other PORTA pins are multiplexed with
the analog V
pins, RA<5,3:0>, as A/D Converter inputs is selected
by clearing or setting the appropriate PCFG control bits
in the ANCON0 register.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
OSC2/CLKO/RA6
serve as the external circuit connections for the
external (primary) oscillator circuit (HS and HSPLL
Oscillator modes), or the external clock input (EC and
ECPLL Oscillator modes). In these cases, RA6 and
RA7 are not available as digital I/O, and their
corresponding TRIS and LAT bits are read as ‘0’.
DS39778D-page 132
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1: RA5 (RA5/PMD4/AN4) is multiplexed as
U-0
—
2: RA5 and RA3:RA0 are configured as
PORTA, TRISA and
LATA Registers
an analog input in all devices and Parallel
Master Port data in 80-pin devices.
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
REF
Unimplemented: Read as ‘0’
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
+ and V
U-0
and
—
PADCFG1: I/O PAD CONFIGURATION CONTROL REGISTER
REF
OSC1/CLKI/RA7
- inputs. The operation of
W = Writable bit
‘1’ = Bit is set
U-0
—
normally
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
For INTIO and INTPLL Oscillator modes (FOSC2 Con-
figuration bit is ‘0’), either RA7 or both RA6 and RA7
automatically become available as digital I/O, depend-
ing on the oscillator mode selected. When RA6 is not
configured as a digital I/O, in these cases, it provides a
clock output at F
tions for RA6 and RA7, based on oscillator mode, is
provided in Table 10-3. For these pins, the correspond-
ing PORTA, TRISA and LATA bits are only defined
when the pins are configured as I/O.
TABLE 10-3:
EXAMPLE 10-1:
CLRF
CLRF
BSF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
Legend: CLKO = F
U-0
—
(FOSC2:FOSC0 Configuration)
PORTA
LATA
WDTCON,ADSHR ; Enable write/read to
1Fh
ANCON0
WDTCON,ADSHR ; Disable write/read
0CFh
TRISA
Oscillator Mode
INTPLL1 (011)
INTPLL2 (010)
I/O = digital port.
INTIO1 (001)
INTIO2 (000)
U-0
—
OSC
FUNCTION OF RA7:RA6 IN
INTIO AND INTPLL MODES
/4. A list of the possible configura-
OSC
INITIALIZING PORTA
© 2009 Microchip Technology Inc.
; Initialize PORTA by
; clearing output
; data latches
; Alternate method to
; clear
; the shared SFR
; Configure A/D
; for digital inputs
; to the shared SFR
; Value used to
; initialize
; data direction
; Set RA<3:0> as inputs,
; RA<5:4> as outputs
x = Bit is unknown
/4 clock output;
U-0
—
data latches
CLKO
CLKO
RA6
I/O
I/O
PMPTTL
R/W-0
RA7
I/O
I/O
I/O
I/O
bit 0