PIC18F87J11-I/PT Microchip Technology, PIC18F87J11-I/PT Datasheet - Page 146

• Manufacturer Part Number: PIC18F87J11-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J11-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164136 - DEVELOPMENT KIT FOR PIC18AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
10.8
PORTG is a 5-bit wide, bidirectional port. All pins on
PORTG are digital only and tolerate voltages up to
5.5V.
PORTG is multiplexed with EUSART2 functions
(Table 10-16). PORTG pins have Schmitt Trigger input
buffers. PORTG is also multiplexed with address and
control functions of the Parallel Master Port.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
DS39778D-page 146
PORTF
LATF
TRISF
ANCON0
ANCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
Note 1:
Name
PORTG, TRISG and
LATG Registers
(1)
(1)
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
PCFG15
TRISF7
PCFG7
LATF7
Bit 7
RF7
PCFG14
TRISF6
PCFG6
LATF6
Bit 6
RF6
PCFG13
TRISF5
LATF5
Bit 5
RF5
—
PCFG12
TRISF4
PCFG4
LATF4
Bit 4
RF4
PCFG11
TRISF3
PCFG3
LATF3
Bit 3
RF3
Although the port itself is only five bits wide,
PORTG<7:5> bits are still implemented. These are
used to control the weak pull-ups on the I/O ports asso-
ciated with the external memory bus (PORTD, PORTE
and PORTJ). Setting these bits enables the pull-ups.
Since these are control bits and are not associated with
port I/O, the corresponding TRISG and LATG bits are
not implemented.
EXAMPLE 10-7:
CLRF
CLRF
MOVLW
MOVWF
PCFG10
TRISF2
PCFG2
LATF2
Bit 2
PORTG
LATG
04h
TRISG
RF2
; Initialize PORTG by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as outputs
TRISF1
PCFG1
PCFG9
LATF1
Bit 1
RF1
INITIALIZING PORTG
© 2009 Microchip Technology Inc.
PCFG0
PCFG8
Bit 0
—
—
—
on Page:
Values
Reset
61
60
60
59
59