PIC18F4580T-I/PT Microchip Technology, PIC18F4580T-I/PT Datasheet - Page 190

• Manufacturer Part Number: PIC18F4580T-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18F2480/2580/4480/4580
TABLE 17-3:
DS39637D-page 190
INTCON
RCON
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
TRISB
TRISC
TRISD
TMR1L
TMR1H
T1CON
TMR2
T2CON
PR2
TMR3L
TMR3H
T3CON
ECCPR1L
ECCPR1H
ECCP1CON
ECCP1AS
ECCP1DEL
Legend:
Note 1:
Name
(1)
2:
3:
(2)
(2)
(2)
(2)
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
These bits are available on PIC18F4X80 devices only.
These bits or registers are unimplemented in PIC18F2X80 devices; always maintain these bit clear.
These bits are available on PIC18F4X80 and reserved on PIC18F2X80 devices.
(2)
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
Timer2 Period Register
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
Enhanced Capture/Compare/PWM Register 1 (LSB)
Enhanced Capture/Compare/PWM Register 1 (MSB)
EPWM1M1 EPWM1M0
ECCPASE ECCPAS2
GIE/GIEH
OSCFIP
OSCFIF
OSCFIE
PRSEN
PSPIP
PSPIE
PSPIF
RD16
RD16
REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
IPEN
Bit 7
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1
T3ECCP1
PEIE/GIEL
SBOREN
CMIP
CMIE
PDC6
CMIF
T1RUN
ADIP
ADIE
Bit 6
ADIF
(3)
(3)
(3)
(2)
(1)
ECCPAS1 ECCPAS0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
T3CKPS1 T3CKPS0 T3CCP1
EDC1B1
TMR0IE
PDC5
RCIP
RCIE
RCIF
Bit 5
—
—
—
—
(2)
EDC1B0
PDC4
INT0IE
TXIP
TXIE
EEIP
EEIF
EEIE
Bit 4
TXIF
RI
(2)
ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
PSSAC1
PDC3
SSPIP
SSPIE
SSPIF
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
TO
(2)
(1)
T3SYNC
PSSAC0 PSSBD1
TMR0IF
CCP1IP
CCP1IE
CCP1IF
HLVDIP
HLVDIF
HLVDIE
PDC2
Bit 2
PD
(2)
TMR1CS
TMR3CS
TMR2IP
TMR2IF
TMR2IE
TMR3IP ECCP1IP
TMR3IF
TMR3IE ECCP1IE
PDC1
© 2009 Microchip Technology Inc.
INT0IF
Bit 1
POR
(2)
(2)
ECCP1IF
PSSBD0
TMR1ON
T2CKPS0
TMR3ON
TMR1IP
TMR1IE
TMR1IF
PDC0
RBIF
Bit 0
BOR
(2)
(2)
(3)
(3)
(3)
on Page:
Values
Reset
56
57
57
57
55
56
58
58
58
57
58
58
58
58
58
56
56
56
56
56
57
57
57
57
57