PIC18F4580T-I/PT Microchip Technology, PIC18F4580T-I/PT Datasheet - Page 457

• Manufacturer Part Number: PIC18F4580T-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FIGURE 28-22:
TABLE 28-25: A/D CONVERSION REQUIREMENTS
© 2009 Microchip Technology Inc.
130
131
132
135
136
Note 1:
Param
No.
A/D DATA
Note 1:
SAMPLE
A/D CLK
2:
3:
4:
5:
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
AMP
GO
Q4
2:
The time of the A/D clock period is dependent on the device frequency and the T
ADRES register may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
50Ω.
On the following cycle of the device clock.
See Section 20.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
If the A/D clock source is selected as RC, a time of T
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 2)
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Amplifier Settling Time (Note 5)
A/D CONVERSION TIMING
Characteristic
(Note 2)
9
DD
to AV
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
8
SS
PIC18F2480/2580/4480/4580
OLD_DATA
or AV
7
SS
. . .
SAMPLING STOPPED
to AV
CY
is added before the A/D clock starts. This allows the SLEEP instruction
CY
Min
0.7
1.4
1.4
—
—
11
—
DD
. . .
1
131
130
cycle.
). The source impedance (R
(Note 4)
25.0
25.0
2
Max
12
—
—
1
3
(1)
(1)
1
Units
T
μs
μs
μs
μs
μs
—
μs
AD
T
V
T
A/D RC mode
V
A/D RC mode
-40°C to +85°C
This may be used if the “new” input
voltage has not changed by more
than 1 LSb (i.e., 5 mV @ 5.12V)
from the last sampled voltage (as
stated on C
OSC
OSC
DD
DD
0
= 2.0V;
= 2.0V;
based, V
based, V
S
AD
) on the input channels is
clock divider.
NEW_DATA
DONE
Conditions
HOLD
DS39637D-page 457
REF
REF
).
T
CY
≥ 3.0V
full range