PIC18F4580T-I/PT Microchip Technology, PIC18F4580T-I/PT Datasheet - Page 484

• Manufacturer Part Number: PIC18F4580T-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18F2480/2580/4480/4580
Timer3 .............................................................................. 163
Timing Diagrams
DS39637D-page 484
PR2 Register .................................................... 173, 179
TMR2 to PR2 Match Interrupt .......................... 173, 179
16-Bit Read/Write Mode ........................................... 165
Associated Registers ....................................... 165, 172
Operation ................................................................. 164
Oscillator .......................................................... 163, 165
Overflow Interrupt ............................................ 163, 165
Special Event Trigger (CCP) .................................... 165
TMR3H Register ...................................................... 163
TMR3L Register ....................................................... 163
A/D Conversion ........................................................ 457
Acknowledge Sequence .......................................... 224
Asynchronous Reception ......................................... 245
Asynchronous Transmission .................................... 242
Asynchronous Transmission (Back-to-Back) ........... 242
Automatic Baud Rate Calculation ............................ 240
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 246
Baud Rate Generator with Clock Arbitration ............ 218
BRG Overflow Sequence ......................................... 240
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 443
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision for Transmit and Acknowledge ........... 225
Capture/Compare/PWM (CCP) ................................ 445
CLKO and I/O .......................................................... 442
Clock Synchronization ............................................. 211
EUSART Synchronous Receive (Master/Slave) ...... 455
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 447
Example SPI Master Mode (CKE = 1) ..................... 448
Example SPI Slave Mode (CKE = 0) ....................... 449
Example SPI Slave Mode (CKE = 1) ....................... 450
External Clock (All Modes except PLL) .................... 440
Fail-Safe Clock Monitor ............................................ 362
First Start Bit Timing ................................................ 219
Full-Bridge PWM Output .......................................... 183
Half-Bridge PWM Output ......................................... 182
High-Voltage Detect (VDIRMAG = 1) ....................... 276
I
I
I
I
I
I
I
I
I
I
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 451
C Bus Start/Stop Bits ............................................. 451
C Master Mode (7 or 10-Bit Transmission) ........... 222
C Master Mode (7-Bit Reception) .......................... 223
C Slave Mode (10-Bit Reception, SEN = 0) .......... 208
C Slave Mode (10-Bit Reception, SEN = 1) .......... 213
C Slave Mode (10-Bit Transmission) ..................... 209
C Slave Mode (7-Bit Reception, SEN = 0) ............ 206
C Slave Mode (7-Bit Reception, SEN = 1) ............ 212
C Slave Mode (7-Bit Transmission) ....................... 207
Normal Operation ............................................. 246
Start Condition ................................................. 227
Condition (Case 1) ........................................... 228
Condition (Case 2) ........................................... 228
(SCL = 0) ......................................................... 227
(SDA only) ........................................................ 226
(Case 1) ........................................................... 229
(Case 2) ........................................................... 229
(Master/Slave) .................................................. 455
Timing Diagrams and Specifications ............................... 440
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 275
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4480/4580) ................... 446
Parallel Slave Port (PSP) Read ............................... 150
Parallel Slave Port (PSP) Write ............................... 150
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 185
PWM Direction Change at Near
PWM Output ............................................................ 173
Repeat Start Condition ............................................ 220
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 247
Slave Synchronization ............................................. 197
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 196
SPI Mode (Slave Mode with CKE = 0) ..................... 198
SPI Mode (Slave Mode with CKE = 1) ..................... 198
Stop Condition Receive or Transmit Mode .............. 224
Synchronous Reception (Master Mode, SREN) ...... 250
Synchronous Transmission ..................................... 248
Synchronous Transmission (Through TXEN) .......... 249
Time-out Sequence on POR w/ PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 444
Transition for Entry to Idle Mode ................................ 44
Transition for Entry to SEC_RUN Mode .................... 41
Transition for Entry to Sleep Mode ............................ 43
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 44
Transition for Wake From Sleep (HSPLL) ................. 43
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 42
A/D Conversion Requirements ................................ 457
AC Characteristics
Capture/Compare/PWM Requirements ................... 445
CLKO and I/O Requirements ................................... 442
EUSART Synchronous Receive Requirements ....... 455
EUSART Synchronous Transmission
2
C Slave Mode General Call Address Sequence
(7 or 10-Bit Address Mode) ............................. 214
Auto-Restart Disabled) .................................... 188
Auto-Restart Enabled) ..................................... 188
100% Duty Cycle ............................................. 185
Timer (OST) and Power-up Timer (PWRT) ..... 443
V
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 360
PRI_RUN Mode ................................................. 42
PRI_RUN Mode (HSPLL) .................................. 41
Internal RC Accuracy ....................................... 441
Requirements .................................................. 455
DD
Rise > T
2
2
C Bus Data ........................................ 453
C Bus Start/Stop Bits ........................ 453
PWRT
© 2009 Microchip Technology Inc.
DD
) ............................................ 53
, V
DD
DD
DD
), Case 1 ...................... 52
), Case 2 ...................... 52
Rise Tpwrt) ................ 52
DD
DD
) ............................ 53
,