PIC18F4580T-I/PT Microchip Technology, PIC18F4580T-I/PT Datasheet - Page 452

• Manufacturer Part Number: PIC18F4580T-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18F2480/2580/4480/4580
TABLE 28-19: I
DS39637D-page 452
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
Symbol
B
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode I
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
T
is released.
R
:
:
:
:
:
STA
DAT
STO
STA
DAT
max. + T
2
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
Start Condition Setup
Time
Start Condition Hold
Time
Data Input Hold Time 100 kHz mode
Data Input Setup Time 100 kHz mode
Stop Condition Setup
Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
SU
2
:
DAT
C™ bus device can be used in a Standard mode I
= 1000 + 250 = 1250 ns (according to the Standard mode I
Characteristic
100 kHz mode
400 kHz mode
MSSP module
100 kHz mode
400 kHz mode
MSSP module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
2
C bus system, but the requirement T
B
B
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification), before the SCL line
Units
μs
μs
μs
μs
ns
ns
ns
ns
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
pF
© 2009 Microchip Technology Inc.
PIC18FXXXX must operate at
a minimum of 1.5 MHz
PIC18FXXXX must operate at
a minimum of 10 MHz
PIC18FXXXX must operate at
a minimum of 1.5 MHz
PIC18FXXXX must operate at
a minimum of 10 MHz
C
10 to 400 pF
C
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission can
start
B
B
is specified to be from
is specified to be from
Conditions
SU
:
DAT
≥ 250 ns