PIC18F4580T-I/PT Microchip Technology, PIC18F4580T-I/PT Datasheet - Page 94

• Manufacturer Part Number: PIC18F4580T-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18F2480/2580/4480/4580
6.3.5
The STATUS register, shown in Register 6-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
If the STATUS register is the destination for an instruc-
tion that affects the Z, DC, C, OV or N bits, the results
of the instruction are not written; instead, the status is
updated according to the instruction performed. There-
fore, the result of an instruction with the STATUS
register as its destination may be different than
intended. As an example, CLRF STATUS will set the Z
bit and leave the remaining Status bits unchanged
(‘000u u1uu’).
REGISTER 6-2:
DS39637D-page 94
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
2:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the
source register.
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of
the source register.
STATUS REGISTER
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude
which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
U-0
—
STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
(2)
U-0
—
(1)
R/W-x
N
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-x
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register, because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 26-2 and
Table 26-3.
OV
Note:
The C and DC bits operate as the borrow
and digit borrow bits respectively in
subtraction.
R/W-x
Z
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-x
DC
(1)
R/W-x
C
(2)
bit 0