PIC18F4580T-I/PT Microchip Technology, PIC18F4580T-I/PT Datasheet - Page 261

• Manufacturer Part Number: PIC18F4580T-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

20.6
Figure 20-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 20-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are set to ‘010’ and selecting a 4 T
acquisition time before the conversion starts.
FIGURE 20-3:
FIGURE 20-4:
© 2009 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
T
Set GO/DONE bit
CY
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D Conversions
1
- T
T
AD
ACQT
Conversion starts
Acquisition
Automatic
2
T
AD
Time
Cycles
1 T
A/D CONVERSION T
A/D CONVERSION T
3
AD
b9
2 T
4
AD
b8
Conversion starts
(Holding capacitor is disconnected)
3 T
1
AD
b7
4 T
b9
2
AD
PIC18F2480/2580/4480/4580
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
b8
3
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
AD
AD
b5
6 T
b7
4
AD
b4
7 T
T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
5
b6
AD
AD
b3
Note:
AD
Cycles
8
b5
wait is required before the next acquisition can
6
conversion
T
AD
b2
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
b4
7
AD
b1
10
b3
T
8
AD
sample.
b0
ACQ
11
ACQ
b2
9
= 0)
= 4 T
10
This
b1
AD
DS39637D-page 261
)
b0
11
means
the