AT89C5131A-PUTUM Atmel, AT89C5131A-PUTUM Datasheet - Page 51

• Manufacturer Part Number: AT89C5131A-PUTUM
• Description: IC 8051 MCU FLASH 32K USB 32QFN
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-PUTUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Data Ram Size: 1.25 KB
• Number Of Programmable I/os: 34
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Mounting Style: SMD/SMT
• Height: 0.95 mm
• Interface Type: 2-Wire, EUART, SPI, USB
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4337K–USB–04/08
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)
internal data memory. The stack may not be located in the ERAM.
The M0 bit allows to stretch the ERAM timings; if M0 is set, the read and write pulses are
extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For
• The ERAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and
• With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in
• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.
accesses the SFR at location 0A0h (which is P2).
example: MOV atR0, # data where R0 contains 0A0h, accesses the data byte at address
0A0h, rather than P2 (whose address is 0A0h).
MOVX instructions. This part of memory which is physically located on-chip, logically
occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a
part of the available ERAM as explained in Table 12-1. This can be useful if external
peripherals are mapped at addresses already used by the internal ERAM.
combination with any of the registers R0, R1 of the selected bank or DPTR. An access to
ERAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =
0, MOVX atR0, # data where R0 contains 0A0H, accesses the ERAM at address 0A0H rather
than external memory. An access to external data memory locations higher than the
accessible size of the ERAM will be performed with the MOVX DPTR instructions in the same
way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7
as write and read timing signals. Accesses to ERAM above 0FFH can only be done by the
use of DPTR.
MOVX at Ri will provide an eight-bit address multiplexed with data on Port0 and any output
port pins can be used to output higher order address bits. This is to provide the external
paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-
order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight
address bits (DPL) with data. MOVX at Ri and MOVX @DPTR will generate either read or
write signals on P3.6 (WR) and P3.7 (RD).
Table 12-2.
DPU
7
Number
Bit
7
6
AUXR Register
AUXR - Auxiliary Register (8Eh)
6
-
Mnemonic
DPU
Bit
-
M0
5
Description
Disable Weak Pull Up
Cleared to enabled weak pull up on standard Ports.
Set to disable weak pull up on standard Ports.
Reserved
The value read from this bit is indeterminate. Do not set this bit
4
-
XRS1
3
AT89C5130A/31A-M
XRS0
2
EXTRAM
1
AO
0
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