ST72F63BK4B1 STMicroelectronics, ST72F63BK4B1 Datasheet - Page 82

• Manufacturer Part Number: ST72F63BK4B1
• Description: IC MCU 8BIT 16K FLASH 32-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BK4B1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 8 Channel / 8 bit, 12 Channel
• For Use With: 497-5521 - EVAL BOARD LOW SPEED USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

On-chip peripherals
11.3.4
82/186
Functional description
The block diagram of the Serial Control Interface, is shown in
dedicated registers:
●
●
●
Refer to the register descriptions in
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving “0”s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 42. Word length programming
Two control registers (SCICR1 & SCICR2)
A status register (SCISR)
A baud rate register (SCIBRR)
9-bit Word length (M bit is set)
Start
Bit
8-bit Word length (M bit is reset)
Start
Bit
Bit0
Bit0
Bit1
Figure
Bit1
Data Frame
Idle Frame
Break Frame
Data Frame
Idle Frame
Break Frame
Bit2
Bit2
41).
Bit3
Doc ID 7516 Rev 8
Bit3
Section 11.3.7
Bit4
Bit4
Bit5
Bit5
Bit6
Bit6
for the definitions of each bit.
Possible
Bit7
Parity
Bit7
Bit
Possible
Parity
Bit8
Bit
Stop
Bit
Stop
Figure 41
Bit
Extra
Start
Next
Start
Bit
Bit
’1’
Extra
Next Data Frame
Next
Start
Start
Bit
Bit
’1’
Start
Bit
Next Data Frame
Start
Bit
It contains 6
ST7263Bxx