MC908LJ24CPBER

Manufacturer Part NumberMC908LJ24CPBER
DescriptionIC MCU 24K FLASH 4/8MHZ 64-LQFP
ManufacturerFreescale Semiconductor
SeriesHC08
MC908LJ24CPBER datasheet
 

Specifications of MC908LJ24CPBER

Core ProcessorHC08Core Size8-Bit
Speed8MHzConnectivityI²C, IRSCI, SPI
PeripheralsLCD, LVD, POR, PWMNumber Of I /o40
Program Memory Size24KB (24K x 8)Program Memory TypeFLASH
Ram Size768 x 8Voltage - Supply (vcc/vdd)3 V ~ 5.5 V
Data ConvertersA/D 6x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case64-LQFP
Controller Family/seriesHC08No. Of I/o's40
Ram Memory Size768ByteCpu Speed8MHz
No. Of Timers2Embedded Interface TypeI2C, SCI, SPI
Rohs CompliantYesProcessor SeriesHC08LJ
CoreHC08Data Bus Width8 bit
Data Ram Size768 BInterface TypeSCI, SPI
Maximum Clock Frequency8 MHzNumber Of Programmable I/os48
Number Of Timers4Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierFSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature- 40 COn-chip Adc10 bit, 6 Channel
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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MC68HC908LJ24
MC68HC908LK24
Data Sheet
M68HC08
Microcontrollers
Rev. 2.1
MC68HC908LJ24/D
August 16, 2005
freescale.com

MC908LJ24CPBER Summary of contents

  • Page 1

    MC68HC908LJ24 MC68HC908LK24 Data Sheet M68HC08 Microcontrollers Rev. 2.1 MC68HC908LJ24/D August 16, 2005 freescale.com ...

  • Page 2

    ...

  • Page 3

    ... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. This product incorporates SuperFlash® technology licensed from SST. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor © Freescale, Inc., 2005 Data Sheet 3 ...

  • Page 4

    ... Revision History Revision Date Level 8/2003 2 First general release. Data Sheet 4 Revision History Description MC68HC908LJ24/LK24 — Rev. 2.1 Page Number(s) — Freescale Semiconductor ...

  • Page 5

    ... Section 15. Multi-Master IIC Interface (MMIIC 319 Section 16. Analog-to-Digital Converter (ADC 333 Section 17. Liquid Crystal Display (LCD) Driver . . . . . 349 Section 18. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 375 Section 19. External Interrupt (IRQ 401 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Interface Module (IRSCI 245 List of Sections List of Sections Data Sheet 5 ...

  • Page 6

    ... Section 21. Computer Operating Properly (COP 415 Section 22. Low-Voltage Inhibit (LVI 421 Section 23. Break Module (BRK 427 Section 24. Electrical Specifications 435 Section 25. Mechanical Specifications . . . . . . . . . . . . . 451 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 457 Appendix A. MC68HC908LK24 459 Data Sheet 6 MC68HC908LJ24/LK24 — Rev. 2.1 List of Sections Freescale Semiconductor ...

  • Page 7

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Power Supply Pins (V DD Analog Power Supply Pin (V LCD Bias Voltage (V LCD Oscillator Pins (OSC1 and OSC2) ...

  • Page 8

    ... FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 72 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 73 FLASH Program Operation .74 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 77 Section 5. Configuration Registers (CONFIG) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Configuration Register 1 (CONFIG1 Configuration Register 2 (CONFIG2 Table of Contents MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 9

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Wait Mode ...

  • Page 10

    ... CGM CPU Interrupt (CGMINT 125 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .128 PLL Multiplier Select Registers . . . . . . . . . . . . . . . . . . . . . 130 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .131 PLL Reference Divider Select Register . . . . . . . . . . . . . . . 132 Table of Contents ) . . . . . . . . . . . . . . . . . . . . . . 124 ) . . . . . . . . . . . . . . . . . . . . . 124 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 11

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Interrupts .133 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 CGM During Break Interrupts 134 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 135 Acquisition/Lock Time Definitions .135 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 135 Choosing a Filter ...

  • Page 12

    ... Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Security 177 ROM-Resident Routines 179 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 MON_PRGRNGE 185 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 EE_WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 EE_READ 191 Table of Contents MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 13

    ... TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 211 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 212 11.10.5 TIM Channel Registers 215 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 11. Timer Interface Module (TIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Pin Name Conventions ...

  • Page 14

    ... Chronograph Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Timebase Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 RTC Clock Calibration and Compensation . . . . . . . . . . . . . . . 225 Calibration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 RTC Register and Bit Write Protection . . . . . . . . . . . . . . . . . . 227 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 Table of Contents MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 15

    ... I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.10.1 PTB0/TxD (Transmit Data 267 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 13. Infrared Serial Communications Interface Module (IRSCI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Infrared Functional Description ...

  • Page 16

    ... Clock Phase and Polarity Controls 293 Transmission Format When CPHA = 294 Transmission Format When CPHA = 296 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 297 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Interrupts .304 Table of Contents MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 17

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 15. Multi-Master IIC Interface (MMIIC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Multi-Master IIC Address Register (MMADR 321 Multi-Master IIC Control Register (MMCR 323 Multi-Master IIC Master Control Register (MIMCR) ...

  • Page 18

    ... Pin Name Conventions and I/O Register Addresses . . . . . . . 350 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 LCD Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 LCD Voltages ( LCD LCD1 LCD Cycle Frame 355 Fast Charge and Low Current . . . . . . . . . . . . . . . . . . . . . . 356 Contrast Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Table of Contents ) . . . . . . . . . . . . . . . . . . . . . 341 ). . . . . . . . . . . . . . . . . . . . . 341 ). . . . . . . . . . . . . 341 REFH ) . . . . . . . . . . . . . 341 REFL , 355 LCD2 LCD3 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 19

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 BP0–BP3 (Backplane Drivers 359 FP0–FP32 (Frontplane Drivers 361 Seven Segment Display Connection . . . . . . . . . . . . . . . . . . . 365 I/O Registers 368 LCD Control Register (LCDCR) ...

  • Page 20

    ... Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . 412 Keyboard Status and Control Register 412 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 413 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 414 Table of Contents MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 21

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 21. Computer Operating Properly (COP) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417 Power-On Reset 417 Internal Reset ...

  • Page 22

    ... SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 434 Section 24. Electrical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Functional Operating Range 437 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 438 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 439 5V Control Timing .440 Table of Contents MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 23

    ... A.1 A.2 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 3.3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Section 25. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 64-Pin Low-Profile Quad Flat Pack (LQFP 452 64-Pin Quad Flat Pack (QFP 453 80-Pin Low-Profile Quad Flat Pack (LQFP 454 80-Pin Quad Flat Pack (QFP) ...

  • Page 24

    ... A.5.1 A.5.2 A.5.3 A.5.4 A.6 Data Sheet 24 Oscillator .460 Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 461 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 461 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . .462 3.3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . 462 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 Table of Contents MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 25

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Title MC68HC908LJ24 Block Diagram 80-Pin QFP and LQFP Pin Assignment . . . . . . . . . . . . . . . . . . 42 64-pin QFP and LQFP Pin Assignment . . . . . . . . . . . . . . . . . . 43 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .52 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 70 FLASH Control Register (FLCR) ...

  • Page 26

    ... SIM I/O Register Summary .142 CGM Clock Signals 143 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 List of Figures Page MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 27

    ... Alarm Minute Register (ALMR 240 12-12 Alarm Hour Register (ALHR 240 12-13 Second Register (SECR 241 12-14 Minute Register (MINR 241 12-15 Hour Register (HRR 242 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Title List of Figures List of Figures Page Data Sheet ...

  • Page 28

    ... Transmission Format (CPHA = 295 14-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 14-6 Transmission Format (CPHA = 296 14-7 Transmission Start Delay (Master 298 14-8 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 299 14-9 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .301 Data Sheet 28 Title MC68HC908LJ24/LK24 — Rev. 2.1 List of Figures Page Freescale Semiconductor ...

  • Page 29

    ... Duty LCD Backplane Driver Waveforms 360 17-8 Static LCD Frontplane Driver Waveforms 361 17-9 1/3 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . . 362 17-10 1/4 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . . 363 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Title Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 331 List of Figures List of Figures ...

  • Page 30

    ... Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 18-23 Port F LED Control Register (LEDF 399 19-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 403 19-2 IRQ I/O Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . 403 Data Sheet 30 Title 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . 366 List of Figures Page MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 31

    ... Quad Flat Pack (Case No. 840B 453 25-3 80-Pin Low-Profile Quad Flat Pack (Case No. 917 454 25-4 80-Pin Quad Flat Pack (Case No. 841B 455 A-1 A-2 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Title MC68HC908LK24 Crystal Oscillator Connection . . . . . . . . . 460 MC68HC908LK24 Configuration Register 1 (CONFIG1 460 List of Figures List of Figures ...

  • Page 32

    ... List of Figures Data Sheet 32 MC68HC908LJ24/LK24 — Rev. 2.1 List of Figures Freescale Semiconductor ...

  • Page 33

    ... RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 176 10-10 Summary of ROM-Resident Routines . . . . . . . . . . . . . . . . . . 179 10-11 PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 10-12 ERARNGE Routine 183 10-13 LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Title Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 FLASH Block Protect Register to Physical Address . . . . . . . . . 78 LVI Trip Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Opcode Map ...

  • Page 34

    ... SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . 316 15-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15-2 Baud Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 16-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 16-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 16-3 ADC Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 Data Sheet 34 Title MC68HC908LJ24/LK24 — Rev. 2.1 List of Tables Page Freescale Semiconductor ...

  • Page 35

    ... Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 445 24-13 CGM Electrical Specifications 445 24-14 5V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 24-15 3.3V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 24-16 FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . . 450 26-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Title List of Tables List of Tables Page Data Sheet 35 ...

  • Page 36

    ... List of Tables Table A-1 A-2 A-3 A-4 A-5 Data Sheet 36 Title 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 461 3.3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 461 5V Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 462 3.3V Oscillator Specifications 462 MC68HC908LK24 Order Numbers 462 List of Tables Page MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 37

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Power Supply Pins (V DD Analog Power Supply Pin (V LCD Bias Voltage (V LCD Oscillator Pins (OSC1 and OSC2) ...

  • Page 38

    ... Selectable periodic interrupt requests for seconds, minutes security feature is absolutely secure. However, Freescale strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 38 hours, days, 2-Hz, 4-Hz, 8-Hz, 16-Hz, and 128-Hz General Description 1 feature MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 39

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor – Temperature drift compensation by user software and external temperature sensor with temperature drift profile from crystal vendor Serial communications interface module (SCI) with infrared (IR) encoder/decoder Inter-IC Bus interface module (IIC) ...

  • Page 40

    ... Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.4 MCU Block Diagram Figure 1-1 Data Sheet 40 LCD driver shows the structure of the MC68HC908LJ24. General Description MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 41

    ... Pin contains integrated pullup device if configured as KBI. † High current sink pin, 15mA. # Pins available on 80-pin packages only. Figure 1-1. MC68HC908LJ24 Block Diagram MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor INTERNAL BUS KEYBOARD INTERRUPT MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE 2-CHANNEL TIMER INTERFACE ...

  • Page 42

    ... PTF4 18 PTE0/FP11 19 PTE1/FP12 20 Figure 1-2. 80-Pin QFP and LQFP Pin Assignment Data Sheet 42 MC68HC908LJ24/LK24 — Rev. 2.1 General Description VREFL 60 VREFH 59 PTB7/ADC5 58 PTB6/ADC4 57 PTA7/ADC3 56 PTA6/ADC2 55 PTA5/ADC1 54 PTA4/ADC0 53 FP30 52 FP29 51 PTA3/KBI3 50 PTA2/KBI2 49 PTA1/KBI1 48 PTA0/KBI0 47 FP28 46 FP27 45 PTC7/FP26 44 PTC6/FP25 43 PTC5/FP24 42 PTD0/SS/CALIN 41 Freescale Semiconductor ...

  • Page 43

    ... FP8 10 PTD6/KBI6/SCL 11 PTD7/KBI7/SDA 12 FP9 13 FP10 14 PTE0/FP11 15 PTE1/FP12 16 Figure 1-3. 64-pin QFP and LQFP Pin Assignment MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Pins not available on 64-LQFP package: PTF7 FP32 PTF6 FP31 PTF5 FP30 PTF4 FP29 PTF3 FP28 PTF2 FP27 PTF1 PTF0 VLCD Internal PTF7– ...

  • Page 44

    ... DDA MCU 0.1 µF C1(a) + C2(a) NOTE: Component values shown V DD represent typical applications. Figure 1-4. Power Supply Bypassing General Description Figure 1-4 must be grounded for SS . For maximum noise DD Figure 1-4). V DDA 0.1 µF C1(b) + C2( MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 45

    ... See 1.6.8 ADC Voltage High Reference Pin (V V REFH See MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ) LCD is the bias voltage supply for the LCD driver module. Connect the pin to the same voltage potential as V via a separate trace and place bypass capacitors LCD Driver ...

  • Page 46

    ... PTD3/SPSCK/CALOUT–PTD0/SS/CALIN are shared with the SPI and RTC modules. Data Sheet 46 ) REFL is the voltage input pin for the ADC voltage low reference. 18.5 Port 18.6 Port D. General Description ). REFL 18.3 Port 18.4 Port B. C. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor A. ...

  • Page 47

    ... BP0–BP2 are the LCD backplane driver pins and FP1– FP10 and FP27–FP32 are the frontplane driver pins. FP0/BP3 is the shared driver pin between FP0 and BP3. See MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 18.7 Port 18.8 Port F. Section 17. Liquid Crystal Display (LCD) ...

  • Page 48

    ... General Description Data Sheet 48 MC68HC908LJ24/LK24 — Rev. 2.1 General Description Freescale Semiconductor ...

  • Page 49

    ... Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset. In the memory map document, unimplemented locations are shaded. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 49 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Input/Output (I/O) Section Figure ...

  • Page 50

    ... FLASH block protect register, FLBPR (FLASH register) • $FFFF; COP control register, COPCTL Data registers are shown in locations. Data Sheet 50 Figure 2-2 and in register figures in this document, Figure 2-2, Table 2-1 MC68HC908LJ24/LK24 — Rev. 2.1 Memory Map is a list of vector Freescale Semiconductor ...

  • Page 51

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor $0000 I/O Registers ↓ 128 Bytes $007F $0080 ↓ 768 Bytes $037F $0380 Unimplemented ↓ 35,968 Bytes $8FFF $9000 User FLASH Memory ↓ 24,576 Bytes $EFFF $F000 Unimplemented ↓ 3,072 Bytes $FBFF $FC00 Monitor ROM 1 ↓ ...

  • Page 52

    ... PTB1 PTB0 PTC3 PTC2 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 PTE3 PTE2 PTE1 PTE0 DDRE3 DDRE2 DDRE1 DDRE0 Reserved MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 53

    ... Read: SPI Data Register $0012 Write: (SPDR) Reset: Read: SCI Control Register 1 $0013 Write: (SCC1) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 13) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit PTF7 PTF6 PTF5 PTF4 DDRF7 DDRF6 DDRF5 DDRF4 ...

  • Page 54

    ... Memory Map Bit RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 CKTST TNP1 TNP0 IREN KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 PCEH PCEL LVISEL1 LVISEL0 †† †† Reserved MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 55

    ... Timer 1 Channel 0 Status $0025 and Control Register Write: (T1SC0) Reset: Read: Timer 1 Channel 0 $0026 Register High Write: (T1CH0H) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 13) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit COPRS LVISTOP LVIRSTD LVIPWRD TOF ...

  • Page 56

    ... TOF 0 TOIE TSTOP 0 TRST Bit Bit Bit Bit CH0F CH0IE MS0B MS0A Unimplemented Memory Map Bit Bit ELS1B ELS1A TOV1 CH1MAX Bit Bit PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Reserved MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 57

    ... Reset: Read: PLL Multiplier Select $0039 Register Low Write: (PMSL) Reset: Read: PLL VCO Range Select $003A Register Write: (PMRS) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 13) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit Bit Bit CH1F 0 ...

  • Page 58

    ... RTCE CHRCLR †† Unimplemented Memory Map Bit 0 RDS3 RDS2 RDS1 RDS0 ADCH3 ADCH2 ADCH1 ADCH0 ADx ADx ADx ADx ADx ADx ADx ADx MODE1 MODE0 OUTF0 RTCWE1 RTCWE0 MINIE SECIE TB1IE TB2IE TBH Reserved MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 59

    ... Write: (MTHR) Reset: Read: Year Register $004C Write: (YRR) Reset: Read: Day-Of-Week Register $004D Write: (DOWR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 13) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit ALMF CHRF DAYF HRF AM5 AM4 ...

  • Page 60

    ... CHR1 CHR0 DUTY0 LCLK2 LCLK1 LCLK0 LCCON3 LCCON2 LCCON1 LCCON0 F0B3 F0B2 F0B1 F0B0 F2B3 F2B2 F2B1 F2B0 F4B3 F4B2 F4B1 F4B0 F6B3 F6B2 F6B1 F6B0 F8B3 F8B2 F8B1 F8B0 F10B3 F10B2 F10B1 F10B0 Reserved MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 61

    ... Read: LCD Data Register 15 $0060 Write: (LDAT15) Reset: Read: LCD Data Register 16 $0061 Write: (LDAT16) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 13) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit F13B3 F13B2 F13B1 F13B0 F15B3 F15B2 F15B1 F15B0 ...

  • Page 62

    ... MMTD6 MMTD5 MMTD4 MMRD6 MMRD5 MMRD4 Unimplemented Memory Map Bit 0 F32B3 F32B2 F32B1 F32B0 MMRW MMBR2 MMBR1 MMBR0 MMAD3 MMAD2 MMAD1 MMEXTAD MMTXAK REPSEN MMTXBE MMRXBF MMTD3 MMTD2 MMTD1 MMTD0 MMRD3 MMRD2 MMRD1 MMRD0 Reserved MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 63

    ... Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: $FE07 Reserved Write: Reset: Read: FLASH Control Register $FE08 Write: (FLCR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 13) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit POR PIN COP ILOP BCFE R ...

  • Page 64

    ... LVIIF 0 LVIIE LVIIACK BPR7 BPR6 BPR5 BPR4 Unaffected by reset; $FF when blank Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented Memory Map Bit Bit Bit BPR3 BPR2 BPR1 BPR0 R = Reserved MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 65

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 2-1. Vector Addresses Priority INT Flag Address Lowest $FFD8 IF18 $FFD9 $FFDA IF17 $FFDB $FFDC IF16 $FFDD $FFDE IF15 $FFDF $FFE0 IF14 $FFE1 $FFE2 IF13 $FFE3 $FFE4 IF12 $FFE5 $FFE6 IF11 $FFE7 $FFE8 IF10 ...

  • Page 66

    ... Memory Map Data Sheet 66 MC68HC908LJ24/LK24 — Rev. 2.1 Memory Map Freescale Semiconductor ...

  • Page 67

    ... RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Random-Access Memory (RAM) Data Sheet 67 ...

  • Page 68

    ... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Data Sheet 68 Random-Access Memory (RAM) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 69

    ... This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 4. FLASH Memory (FLASH) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 FLASH Page Erase Operation ...

  • Page 70

    ... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 70 Bit BPR7 BPR6 BPR5 BPR4 Unaffected by reset; $FF when blank = Unimplemented FLASH Memory (FLASH Bit 0 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 1 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 71

    ... PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor $FE08 Bit ...

  • Page 72

    ... RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Data Sheet 72 (min. 10µs). nvs (1ms). erase (5µs). nvh (1µs), the memory can be accessed in read mode rcv MC68HC908LJ24/LK24 — Rev. 2.1 FLASH Memory (FLASH) Freescale Semiconductor ...

  • Page 73

    ... FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor register. address range. (10µs). nvs (4ms) ...

  • Page 74

    ... Data Sheet 74 (Figure 4-3 shows a flowchart of the programming (10µs). nvs (5µs). pgs (30µs). prog (5µs). nvh (1µs), the memory can be accessed in read mode rcv max. FLASH Memory (FLASH) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 75

    ... This row program algorithm assumes the row programmed are initially erased. Figure 4-3. FLASH Programming Flowchart MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH location within the address range of the row to ...

  • Page 76

    ... It can only be erased using a mass erase operation. NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit Data Sheet 76 MC68HC908LJ24/LK24 — Rev. 2.1 FLASH Memory (FLASH) Freescale Semiconductor ...

  • Page 77

    ... FLASH memory, at $FFFF. With this mechanism, the protect start address can be $XX00 or $XX80 (at page boundaries — 128 bytes) within the FLASH memory. Examples of protect start address is shown in MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor $FFCF Bit ...

  • Page 78

    ... The entire FLASH memory is NOT protected. MC68HC908LJ24/LK24 — Rev. 2.1 FLASH Memory (FLASH) (1) (2) (2) Freescale Semiconductor ...

  • Page 79

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Configuration Register 1 (CONFIG1 Configuration Register 2 (CONFIG2 Computer operating properly module (COP) 18 COP timeout period (2 – 2 Low-voltage inhibit (LVI) module power LVI module reset ...

  • Page 80

    ... POR. Data Sheet 80 Bit STOP_ STOP_ PEE DIV2CLK IRCDIS XCLKEN COPRS LVISTOP LVIRSTD LVIPWRD †† Unimplemented and Figure 5-3. Configuration Registers (CONFIG Bit 0 PCEH PCEL LVISEL1 LVISEL0 †† †† SSREC STOP COPD MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 81

    ... LVIRSTD — LVI Reset Disable LVIRSTD disables the reset signal from the LVI module. (See Section 22. Low-Voltage Inhibit LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. (See Inhibit MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor $001F Bit COPRS LVISTOP LVIRSTD LVIPWRD ...

  • Page 82

    ... Reset by POR only. Data Sheet 82 (COP).) $001D Bit STOP_ STOP_ PEE DIV2CLK IRCDIS XCLKEN Figure 5-3. Configuration Register 2 (CONFIG2) Configuration Registers (CONFIG) Section 21. Computer Bit 0 PCEH PCEL LVISEL1 LVISEL0 †† †† MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 83

    ... DIV2CLK bit has no effect when the BCS=1 in the PLL control register (CGMVCLK selected and divide-by-2 always enabled). Reset clears this bit. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 1 = PTE0/FP11–PTE7/FP18 pins configured as LCD frontplane driver pins: FP11–FP18 0 = PTE0/FP11–PTE7/FP18 pins configured as standard I/O pins: PTE0– ...

  • Page 84

    ... LVI voltage trip points for each of Table 5-1. LVI Trip Point Selection LVISEL1 LVISEL0 Notes: 1. Default setting after a power-on-reset. Configuration Registers (CONFIG) (LVI).) The voltage mode . See Section 24. DD Operating Mode Reserved (1) 3.3V 5V Reserved MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 85

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Wait Mode ...

  • Page 86

    ... Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes • Low-power stop and wait modes Data Sheet 86 MC68HC908LJ24/LK24 — Rev. 2.1 Central Processor Unit (CPU) Freescale Semiconductor ...

  • Page 87

    ... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor shows the five CPU registers. CPU registers are not part Figure 6-1 ...

  • Page 88

    ... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Read: Write: Reset: Data Sheet 88 Bit Indeterminate Figure 6-3. Index Register (H:X) Bit Figure 6-4. Stack Pointer (SP) Central Processor Unit (CPU) Bit Bit MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 89

    ... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit ...

  • Page 90

    ... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Data Sheet 90 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) Central Processor Unit (CPU Bit MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 91

    ... Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result ...

  • Page 92

    ... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock. Data Sheet 92 MC68HC908LJ24/LK24 — Rev. 2.1 Central Processor Unit (CPU) Freescale Semiconductor ...

  • Page 93

    ... Opcode Map The opcode map is provided in MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. ...

  • Page 94

    ... SP2 9EDB IMM DIR EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...

  • Page 95

    ... Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC rel ? ( ⊕ ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← ...

  • Page 96

    ... DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 Freescale Semiconductor ...

  • Page 97

    ... EOR opr EOR opr,X Exclusive OR M with A EOR opr,X EOR ,X EOR opr,SP EOR opr,SP MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← ...

  • Page 98

    ... IX1 SP1 9EE6 ff 4 SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 44 1 INH 54 1 IX1 SP1 9E64 ff 5 Freescale Semiconductor ...

  • Page 99

    ... RORA RORX Rotate Right through Carry ROR opr,X ROR ,X ROR opr,SP RSP Reset Stack Pointer MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← ...

  • Page 100

    ... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 SP2 9ED0 ee ff Freescale Semiconductor ...

  • Page 101

    ... Indexed, 8-bit offset, post increment addressing mode IX2 Indexed, 16-bit offset addressing mode M Memory location N Negative bit MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← ...

  • Page 102

    Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 ...

  • Page 103

    ... MCU sub-systems. The oscillator module consist of two types of oscillator circuits: • • MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 7. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Crystal Amplifier Input Pin (OSC1) ...

  • Page 104

    ... Figure 7-1. Oscillator Module Block Diagram Data Sheet 104 7-1. shows the block diagram of the oscillator module. EN INTERNAL RC OSCILLATOR OSC1 OSC2 32.768kHz (typical) Oscillator (OSC) ICLK To SIM, COP CGMRCLK To CGM PLL CGMXCLK To RTC, ADC, LCD, CGM Clock Selection MUX MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 105

    ... Refer to the crystal manufacturer’s data for more information. 7.5 I/O Signals The following paragraphs describe the oscillator I/O signals. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor = 5V) that requires no external components the reference clock Crystal, X (32.768kHz) 1 Fixed capacitor, C ...

  • Page 106

    ... This is buffered signal of CGMXCLK used by the CGM as the phase-locked-loop (PLL) reference clock. 7.6 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. Data Sheet 106 for detail specification of the MC68HC908LJ24/LK24 — Rev. 2.1 Oscillator (OSC) Freescale Semiconductor ...

  • Page 107

    ... Oscillator During Break Mode The oscillator circuits continue to drive CGMXCLK, CGMRCLK, and ICLK when the device enters the break state. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Oscillator (OSC) Oscillator (OSC) Oscillator During Break Mode Data Sheet ...

  • Page 108

    ... Oscillator (OSC) Data Sheet 108 MC68HC908LJ24/LK24 — Rev. 2.1 Oscillator (OSC) Freescale Semiconductor ...

  • Page 109

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Oscillator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Phase-Locked Loop Circuit (PLL 114 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . 116 Manual and Automatic PLL Bandwidth Modes 116 Programming the PLL ...

  • Page 110

    ... Interrupts .133 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 CGM During Break Interrupts 134 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 135 Acquisition/Lock Time Definitions .135 Parametric Influences on Reaction Time . . . . . . . . . . . . . . 135 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Clock Generator Module (CGM) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 111

    ... Figure 8-1 Figure 8-2 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference Low-frequency crystal operation with low-power operation and high-output frequency resolution Programmable prescaler for power-of-two increases in frequency ...

  • Page 112

    ... DIVIDER CGMPCLK Figure 8-1. CGM Block Diagram Clock Generator Module (CGM) To SIM (and COP) T0 RTC, ADC, LCD USER MODE: CGMOUT = B RESET: A CGMOUT A ÷ SIM SIMDIV2 BASE From SIM CLOCK SELECT CIRCUIT DIV2CLK CONFIG2 CGMINT To SIM MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 113

    ... When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Figure 8-2. CGM I/O Register Summary MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit PLLF ...

  • Page 114

    ... Frequency pre-scaler • Modulo VCO frequency divider • Phase detector • Loop filter • Lock detector Data Sheet 114 for detailed description on oscillator Section 12. Real Time Clock (RTC) Clock Generator Module (CGM) for detailed MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 115

    ... CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, f condition based on this comparison. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor is equal to the nominal center-of-range VRS , (38.4 kHz) times a linear factor, L, and a power-of-two NOM ...

  • Page 116

    ... Data Sheet 116 8.6.2 PLL Bandwidth Control 8.4.8 Base Clock Selector 8.6.2 PLL Bandwidth Control for information and precautions on using interrupts.) Clock Generator Module (CGM) Register.) Circuit.) The PLL is Register.) If PLL 8.4.8 Base Clock Selector MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 117

    ... Such systems typically operate well below f BUSMAX MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor The ACQ bit (See 8.6.2 PLL Bandwidth Control read-only indicator of the mode of the filter. (See Acquisition and Tracking ...

  • Page 118

    ... The VCO frequency must be an integer multiple of this rate. Data Sheet 118 (See 8.9 Acquisition/Lock Time ACQ AL P × VCLKDES CGMPCLK Clock Generator Module (CGM) , after entering tracking mode . BUSDES . VCLKDES × P × BUSDES , and the RCLK /R. For RCLK MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 119

    ... Calculate N: 5. Calculate and verify the adequacy of the VCO and bus MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor The relationship between the VCO frequency, f reference frequency, f RCLK f VCLK where N is the integer range multiplier, between 1 and 4095. In cases where desired bus frequency has some tolerance, ...

  • Page 120

    ... VRS f NOM ≤ -------------------------- – VRS VCLK . For proper operation, f VCLKDES VCLKDES VCLK. Clock Generator Module (CGM 38.4kHz NOM    f NOM NOM E × VCLK VRS must be within the VCLK , and f must be as close as VRS MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 121

    ... MHz 32 MHz 32 MHz 32 MHz MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent the VPR bits of the PLL control register (PCTL), program the binary equivalent the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N ...

  • Page 122

    ... PLL, so that the PLL would be disabled and the oscillator clock would be forced as the source of the base clock. Data Sheet 122 8.4.6 Programming the PLL Circuit.) Clock Generator Module (CGM) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 123

    ... PLL performance.) 8.5 I/O Signals The following paragraphs describe the CGM I/O signals. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor shows the external components for the PLL: Bypass capacitor, C BYP Filter network 8 ...

  • Page 124

    ... DDA ) SSA pin to the same voltage potential as the V carefully for maximum noise immunity and place bypass SSA is physically bonded to the V SSA Clock Generator Module (CGM) pin. DD pin. SS pin. SS MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 125

    ... CGM Registers The following registers control and monitor operation of the CGM: • • • • • MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor PLL control register (PCTL) (See 8.6.1 PLL Control Register.) PLL bandwidth control register (PBWC) (See 8.6.2 PLL Bandwidth Control ...

  • Page 126

    ... Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. Data Sheet 126 $0036 Bit PLLF PLLIE PLLON BCS Unimplemented Figure 8-4. PLL Control Register (PCTL) Clock Generator Module (CGM Bit 0 PRE1 PRE0 VPR1 VPR0 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 127

    ... PLLON bit is set. Reset clears these bits. These prescaler bits affects the relationship between the VCO clock and the final system bus clock. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 1 = PLL PLL off Circuit.) Reset clears the BCS bit CGMPCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT 8 ...

  • Page 128

    ... Table 8-2. PRE 1 and PRE0 Programming PRE1 and PRE0 PLL, and 8.6.4 PLL VCO Range Select Table 8-3. VPR1 and VPR0 Programming VPR1 and VPR0 Clock Generator Module (CGM) Prescaler Multiplier 8.4.3 PLL Circuits, 8.4.6 . VRS VCO Power-of-Two Range Multiplier MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 129

    ... PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor $0037 Bit LOCK ...

  • Page 130

    ... Bit Unimplemented $0039 Bit MUL7 MUL6 MUL5 MUL4 PLL.) A value of $0000 in the multiplier select Clock Generator Module (CGM Bit 0 MUL11 MUL10 MUL9 MUL8 Bit 0 MUL3 MUL2 MUL1 MUL0 8.4.3 PLL Circuits and 8.4.6 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 131

    ... VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor $003A Bit ...

  • Page 132

    ... The default divide value recommended for all applications. Data Sheet 132 $003B Bit Unimplemented PLL.) RDS[3:0] cannot be written when the 8.4.7 Special Programming Clock Generator Module (CGM Bit 0 RDS3 RDS2 RDS1 RDS0 8.4.3 PLL Circuits and 8.4.6 Exceptions.) Reset MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 133

    ... PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Interrupts ...

  • Page 134

    ... With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Data Sheet 134 9.8.3 SIM Break Flag Control Clock Generator Module (CGM) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 135

    ... These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Acquisition/Lock Time Specifications Data Sheet ...

  • Page 136

    ... Data Sheet 136 . This frequency is the input to the phase RDV and the R value programmed in the reference divider. XCLK Circuits, 8.4.6 Programming the Register.) 8.9.3 Choosing a Clock Generator Module (CGM) PLL, and 8.6.5 PLL Filter.) . The DDA MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 137

    ... PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in a 32.768kHz reference clock (CGMRCLK). applications requiring better stability. applications where stability is not critical. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 8.9.2 Parametric Influences on Reaction Figure 8-10 Figure 8-10 CGMXFC 10 kΩ 0.01 µF 0.033 µ ...

  • Page 138

    ... Clock Generator Module (CGM) Data Sheet 138 Clock Generator Module (CGM) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 139

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 142 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Clock Start-up from POR or LVI Reset 143 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 144 Reset and System Initialization 144 External Pin Reset ...

  • Page 140

    ... SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 160 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 161 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 162 Figure 9-1. Table 9-1 shows the internal signal names used in this section. System Integration Module (SIM summary of the SIM MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 141

    ... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER ...

  • Page 142

    ... IF4 IF3 IF14 IF13 IF12 IF11 Unimplemented (CGM).) System Integration Module (SIM Bit 0 SBSW Note 0 ILAD 0 LVI IF2 IF1 IF10 IF9 IF8 IF7 IF18 IF17 IF16 IF15 Reserved Figure 9-3. This clock can come Section MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 143

    ... ICLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor CGMXCLK ICLK SYSTEM INTEGRATION MODULE ...

  • Page 144

    ... An internal reset clears the SIM counter (see external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See Data Sheet 144 System Integration Module (SIM) 9.7.2 Stop Mode.) 9.5 SIM Counter), but an 9.8 SIM Registers.) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 145

    ... SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor shows the relative timing. Table 9-2. PIN Bit Set Timing Reset Type ...

  • Page 146

    ... Data Sheet 146 RST PULLED LOW BY MCU 32 CYCLES Figure 9-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR Figure 9-6. Sources of Internal Reset System Integration Module (SIM) 32 CYCLES VECTOR HIGH INTERNAL RESET MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 147

    ... RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, V RST pin disables the COP module. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 4096 32 32 CYCLES CYCLES Figure 9-7 ...

  • Page 148

    ... MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources. Data Sheet 148 voltage falls to the LVI trip falling voltage, V Section 10. Monitor ROM System Integration Module (SIM) . The LVI bit in TRIPF (MON).) When MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 149

    ... External reset has no effect on the SIM counter. (See for details.) The SIM counter is free-running after all reset states. (See 9.4.2 Active Resets from Internal Sources internal reset recovery sequences.) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor System Integration Module (SIM) System Integration Module (SIM) SIM Counter 9.7.2 Stop Mode ...

  • Page 150

    ... SP – – – – CCR SP – – – CCR – 1[15:8] PC – 1[7:0] System Integration Module (SIM) VECT H VECT L START ADDR V DATA H V DATA L OPCODE OPCODE OPERAND MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 151

    ... The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). (See MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Figure 9-10.) FROM RESET BREAK I BIT SET? ...

  • Page 152

    ... H register and then restore it prior to exiting the routine. Data Sheet 152 CLI LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 9-11 Interrupt Recognition Example System Integration Module (SIM) Figure 9-11 BACKGROUND ROUTINE MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 153

    ... Reset: IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Bit 0 and Bit 1 — Always read 0 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 9-3 summarizes the interrupt sources and the interrupt $FE04 Bit 7 6 ...

  • Page 154

    ... LVI Vector (Low) $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) System Integration Module (SIM) Vector MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 155

    ... These flags indicate the presence of interrupt requests from the sources shown in 9.6.1.6 Interrupt Status Register 3 Address: Read: Write: Reset: IF18–IF15 — Interrupt Flags 18–15 These flags indicate the presence of an interrupt request from the source shown in MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor $FE05 Bit IF14 IF13 IF12 ...

  • Page 156

    ... Upon leaving break mode, execution of the second step will clear the flag as normal. Data Sheet 156 (BRK).) The SIM puts the CPU into the System Integration Module (SIM) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 157

    ... If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Figure 9-16 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Figure 9-15 shows the timing for wait mode entry. IAB WAIT ADDR ...

  • Page 158

    ... IDB $A6 $A6 $A6 $01 Figure 9-16. Wait Recovery from Interrupt or Break 32 CYCLES CYCLES $6E0B $A6 $A6 $A6 Figure 9-17. Wait Recovery from Internal Reset System Integration Module (SIM) $00FF $00FE $00FD $00FC $0B $6E 32 RST VCT H RST VCT L MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 159

    ... Figure 9-19. Stop Mode Recovery from Interrupt or Break 9.8 SIM Registers The SIM has three memory-mapped registers: • • • MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Figure 9-18 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA R/W instruction ...

  • Page 160

    ... Figure 9-20. SIM Break Status Register (SBSR) ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register. System Integration Module (SIM Bit 0 SBSW Note 0 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 161

    ... PIN — External Reset Bit COP — Computer Operating Properly Reset Bit ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) LVI — Low-Voltage Inhibit Reset Bit MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor $FE01 Bit POR ...

  • Page 162

    ... MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Data Sheet 162 $FE03 Bit BCFE Reserved System Integration Module (SIM Bit MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 163

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Security ...

  • Page 164

    ... Resident routines for in-circuit programming and EEPROM emulation 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 164 1 MC68HC908LJ24/LK24 — Rev. 2.1 Monitor ROM (MON long as TST , if reset vector is TST , is applied to TST Freescale Semiconductor ...

  • Page 165

    ... MHz). Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when the reset vector is non-zero because entry into monitor mode in this case requires V MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Figure 10-1 shows an example circuit used to enter monitor on IRQ. TST ...

  • Page 166

    ... OSC TST Monitor ROM (MON) RST 0.1 µF HC908LJ24 0.1 µF DDA V LCD V REFH REFL CGMXFC 0.01 µF 10k 0.033 µF OSC1 330k OSC2 6– SW2 (SEE NOTE 1) IRQ D PTA0 PTA1 SW1 A PTC1 B PTA2 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 167

    ... This is to reduce circuit requirements when performing in-circuit programming. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor shows the pin conditions for entering monitor mode. As – The external clock is 4.9152 MHz with PTC1 low or 9.8304 MHz with PTC1 high – ...

  • Page 168

    Table 10-1. Monitor Mode Signal Requirements and Options Address IRQ RST $FFFE/ PTA2 PTA1 PTA0 $FFFF X GND ( TST or V TST ( ...

  • Page 169

    ... MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor If monitor mode was entered as a result of the reset vector being blank (above condition set 2 or 3), the COP is always disabled regardless of the state of IRQ or RST. ...

  • Page 170

    ... Reset Break Vector Vector Vector High Low High $FFFE $FFFF $FFFC $FEFE $FEFF $FEFC Monitor ROM (MON) NORMAL USER MODE Break SWI SWI Vector Vector Vector Low High Low $FFFD $FFFC $FFFD $FEFD $FEFC $FEFD MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 171

    ... PTC1. If monitor mode was entered with V on IRQ, then the internal PLL steps up the external frequency, presumed to be 32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor mode entry require that the reset vector is blank. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor BIT 0 BIT 1 BIT 2 BIT 3 BIT Figure 10-3 ...

  • Page 172

    ... Table 10-3. Monitor Baud Rate Selection IRQ PTC1 Frequency V 0 2.4576 MHz TST V 1 2.4576 MHz TST V X 2.4576 MHz 2.4576 MHz SS MC68HC908LJ24/LK24 — Rev. 2.1 Monitor ROM (MON) Internal Baud Rate (BPS) 9600 9600 9600 9600 Freescale Semiconductor ...

  • Page 173

    ... FROM HOST 3 ECHO Notes: A brief description of each monitor mode command is given in Table 10-4 Description Operand Returned MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor FROM HOST ADDRESS ADDRESS READ READ HIGH HIGH ECHO Notes Echo delay, 2 bit times 2 = Data return delay, 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte ...

  • Page 174

    ... Table 10-6. IREAD (Indexed Read) Command Read next 2 bytes in memory from last address accessed 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence FROM HOST IREAD IREAD DATA ECHO MC68HC908LJ24/LK24 — Rev. 2.1 Monitor ROM (MON) DATA DATA DATA RETURN Freescale Semiconductor ...

  • Page 175

    ... Returned A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Description Operand Returned MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 10-7. IWRITE (Indexed Write) Command Write to last address accessed + 1 Single data byte Data None Opcode ...

  • Page 176

    ... FROM HOST RUN RUN ECHO HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER Figure 10-7. Stack Pointer at Monitor Mode Entry Monitor ROM (MON MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 177

    ... DD RST PTA0 NOTES Echo delay, 2 bit times Data return delay, 2 bit times Wait 1 bit time before sending next byte. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor 4096 + 32 ICLK CYCLES 256 BUS CYCLES (MINIMUM) FROM HOST FROM MCU Figure 10-8. Monitor Mode Entry Timing ...

  • Page 178

    ... FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Data Sheet 178 MC68HC908LJ24/LK24 — Rev. 2.1 Monitor ROM (MON) Freescale Semiconductor ...

  • Page 179

    ... During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 10-10 shows a summary of the ROM-resident Table 10-10. Summary of ROM-Resident Routines ...

  • Page 180

    ... MON_LDRNGE, and EE_READ, data is read from FLASH and stored in this array. Data Sheet 180 R FILE_PTR $XXXX BUS SPEED (BUS_SPD) ADDRESS AS POINTER DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA ARRAY Monitor ROM (MON DATA 0 DATA DATA 1 BLOCK DATA N MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 181

    ... FLASH location $EF00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 10-11. PRGRNGE Routine PRGRNGE Program a range of locations ...

  • Page 182

    ... Indicates 4x bus frequency DS Data size to be programmed DS FLASH start address DS Reserved data array EQU $FC06 EQU $EF00 ORG FLASH MOV #20, BUS_SPD MOV #64, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS BSR INITIALISATION : : LDHX #FILE_PTR JSR PRGRNGE Monitor ROM (MON) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 183

    ... The coding example below is to perform a page erase, from $EF00–$EF7F. The Initialization subroutine is the same as the coding example for PRGRNGE (see ERARNGE MAIN: MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 10-12. ERARNGE Routine ERARNGE Erase a page or the entire array $FCBE 9 bytes ...

  • Page 184

    ... LDRNGE Loads data from a range of locations $FF30 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N 10.6.1 PRGRNGE). EQU $FF30 BSR INITIALIZATION : : LDHX #FILE_PTR JSR LDRNGE : Monitor ROM (MON) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 185

    ... PRGRNGE), except that MON_PRGRNGE returns to the main program via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 10-14. MON_PRGRNGE Routine MON_PRGRNGE Program a range of locations, in monitor mode ...

  • Page 186

    ... Data Sheet 186 Table 10-15. MON_ERARNGE Routine MON_ERARNGE Erase a page or the entire array, in monitor mode $FF2C 11 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) MC68HC908LJ24/LK24 — Rev. 2.1 Monitor ROM (MON) 10.6.2 Freescale Semiconductor ...

  • Page 187

    ... LDRNGE), except that MON_LDRNGE returns to the main program via an SWI instruction. After a MON_LDRNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 10-16. ICP_LDRNGE Routine MON_LDRNGE Loads data from a range of locations, in monitor mode ...

  • Page 188

    ... Table 10-17. EE_WRITE Routine EE_WRITE Emulated EEPROM write. Data size ranges from bytes at a time. $FC00 17 bytes Bus speed (BUS_SPD) (1) Data size (DATASIZE) (2) Starting address (ADDRH) (1) Starting address (ADDRL) Data 1 : Data N MC68HC908LJ24/LK24 — Rev. 2.1 Monitor ROM (MON) Freescale Semiconductor ...

  • Page 189

    ... The data array size is 15 bytes, and the bus speed is 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Figure 10-10). The page control operations PAGE BOUNDARY ...

  • Page 190

    ... Indicates 4x bus frequency DS Data size to be programmed DS FLASH starting address DS Reserved data array EQU $FC00 EQU $EF00 ORG FLASH MOV #20, BUS_SPD MOV #15, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS BSR INITIALISATION : : LHDX #FILE_PTR JSR EE_WRITE Monitor ROM (MON) MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 191

    ... RAM. The initialization subroutine is the same as the coding example for EE_WRITE (see EE_READ MAIN: MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table 10-18. EE_READ Routine EE_READ Emulated EEPROM read. Data size ranges from bytes at a time. $FC03 ...

  • Page 192

    ... FLASH page boundary and the data size 15. If the FLASH page is programmed with a data array with a different size, the EE_READ call will be ignored. Data Sheet 192 MC68HC908LJ24/LK24 — Rev. 2.1 Monitor ROM (MON) Freescale Semiconductor ...

  • Page 193

    ... TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 211 11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . . 212 11.10.5 TIM Channel Registers 215 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Section 11. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Functional Description ...

  • Page 194

    ... External TIM clock input (bus frequency ÷2 maximum) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits Data Sheet 194 MC68HC908LJ24/LK24 — Rev. 2.1 Timer Interface Module (TIM) Figure 11 Freescale Semiconductor ...

  • Page 195

    ... TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels (per timer) are programmable independently as input capture or output compare channels. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Table Table 11-1. Pin Name Conventions T[1,2]CH0 TIM1 ...

  • Page 196

    ... CH1F MS1A Figure 11-1. TIM Block Diagram summarizes the timer registers. Timer Interface Module (TIM) TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T[1,2]CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T[1,2]CH1 LOGIC INTERRUPT LOGIC CH1IE MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 197

    ... Reset: Read: Timer 1 Channel 0 $0027 Register Low Write: (T1CH0L) Reset: Read: Timer 1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: Figure 11-2. TIM I/O Register Summary (Sheet MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit 15 14 ...

  • Page 198

    ... TSTOP 0 TRST Bit Bit Bit Bit CH0F CH0IE MS0B MS0A Bit Indeterminate after reset = Unimplemented Timer Interface Module (TIM Bit Bit Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit 8 MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor ...

  • Page 199

    ... When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. MC68HC908LJ24/LK24 — Rev. 2.1 Freescale Semiconductor Bit Bit 7 ...

  • Page 200

    ... Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Data Sheet 200 11.5.3 Output Compare. The pulses are MC68HC908LJ24/LK24 — Rev. 2.1 Timer Interface Module (TIM) Freescale Semiconductor ...