D12321VF20V Renesas Electronics America, D12321VF20V Datasheet
D12321VF20V
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D12321VF20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2329 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series H8S/2329 HD64F2329B H8S/2328 HD6432328 H8S/2327 HD6432327 H8S/2326 HD64F2326 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev.6.00 Sep. 27, 2007 Page iv of xxx REJ09B0220-0600 ...
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This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data ...
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H8S/2329 Group, H8S/2328 Group Manuals: Document Title H8S/2329 Group, H8S/2328 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual User’s Manuals for Development Tools: Document Title H8S, H8S/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor Compiler Package Ver.6.01 User's Manual ...
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Main Revisions for This Edition Item Page 1.3.1 Pin Arrangement 10 Figure 1.3 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (TFP- 120: Top View) Figure 1.4 Mask ROM 11 Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement ...
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Item Page 1.3.1 Pin Arrangement 15 Figure 1.8 HD64F2329B Pin Arrangement (FP- 128B: Top View) 1.3.3 Pin Functions 26 Table 1.3 Pin Functions 6.3.5 Chip Select 169 Signals Rev.6.00 Sep. 27, 2007 Page viii of xxx REJ09B0220-0600 Revision (See Manual ...
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Item Page 14.2.8 Bit Rate 618 Register (BRR) Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 19.4.1 Features 740 19.13.1 Features 791 19.22.1 Features 849 22.2.6 Flash Memory 977 Characteristics Table 22.22 Flash Memory Characteristics Revision (See Manual ...
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Item Page 22.2.6 Flash Memory 978 Characteristics Table 22.22 Flash Memory Characteristics Appendix F Package 1267 Dimensions Figure F.1 TFP-120 Package Dimensions Figure F.2 FP-128B 1268 Package Dimensions All trademarks and registered trademarks are the property of their respective owners. ...
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Section 1 Overview............................................................................................1 1.1 Overview........................................................................................................................... 1 1.2 Block Diagram .................................................................................................................. 8 1.3 Pin Description.................................................................................................................. 10 1.3.1 Pin Arrangement .................................................................................................. 10 1.3.2 Pin Functions in Each Operating Mode ............................................................... 18 1.3.3 Pin Functions ....................................................................................................... 24 Section 2 CPU....................................................................................................33 2.1 Overview........................................................................................................................... 33 ...
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Bus-Released State............................................................................................... 72 2.8.6 Power-Down State ............................................................................................... 73 2.9 Basic Timing ..................................................................................................................... 73 2.9.1 Overview.............................................................................................................. 73 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 73 2.9.3 On-Chip Supporting Module Access Timing....................................................... 75 2.9.4 External Address Space Access Timing .............................................................. 76 2.10 ...
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Exception Handling Operation............................................................................. 102 4.1.3 Exception Vector Table ....................................................................................... 102 4.2 Reset.................................................................................................................................. 104 4.2.1 Overview.............................................................................................................. 104 4.2.2 Reset Sequence .................................................................................................... 104 4.2.3 Interrupts after Reset............................................................................................ 105 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 105 4.3 Traces................................................................................................................................ ...
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DTC and DMAC Activation by Interrupt ......................................................................... 139 5.6.1 Overview.............................................................................................................. 139 5.6.2 Block Diagram ..................................................................................................... 140 5.6.3 Operation ............................................................................................................. 141 Section 6 Bus Controller....................................................................................143 6.1 Overview........................................................................................................................... 143 6.1.1 Features................................................................................................................ 143 6.1.2 Block Diagram ..................................................................................................... 145 6.1.3 Pin Configuration................................................................................................. 146 ...
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Precharge State Control ....................................................................................... 187 6.5.8 Wait Control ........................................................................................................ 188 6.5.9 Byte Access Control ............................................................................................ 190 6.5.10 Burst Operation.................................................................................................... 192 6.5.11 Refresh Control.................................................................................................... 195 6.6 DMAC Single Address Mode and DRAM Interface (Not supported in the H8S/2321) ... 198 ...
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DMA Control Register (DMACR) ...................................................................... 227 7.2.5 DMA Band Control Register (DMABCR) .......................................................... 231 7.3 Register Descriptions (2) (Full Address Mode) ................................................................ 237 7.3.1 Memory Address Register (MAR)....................................................................... 237 7.3.2 I/O Address Register (IOAR) .............................................................................. 237 7.3.3 Execute Transfer ...
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DTC Mode Register A (MRA) ............................................................................ 314 8.2.2 DTC Mode Register B (MRB)............................................................................. 315 8.2.3 DTC Source Address Register (SAR).................................................................. 317 8.2.4 DTC Destination Address Register (DAR).......................................................... 317 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 318 8.2.6 DTC ...
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Overview.............................................................................................................. 379 9.5.2 Register Configuration......................................................................................... 380 9.5.3 Pin Functions ....................................................................................................... 380 9.6 Port 5................................................................................................................................. 381 9.6.1 Overview.............................................................................................................. 381 9.6.2 Register Configuration......................................................................................... 382 9.6.3 Pin Functions ....................................................................................................... 386 9.7 Port 6................................................................................................................................. 388 9.7.1 Overview.............................................................................................................. 388 9.7.2 Register Configuration......................................................................................... 389 9.7.3 ...
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Port G................................................................................................................................ 435 9.14.1 Overview.............................................................................................................. 435 9.14.2 Register Configuration......................................................................................... 436 9.14.3 Pin Functions ....................................................................................................... 439 Section 10 16-Bit Timer Pulse Unit (TPU)........................................................441 10.1 Overview........................................................................................................................... 441 10.1.1 Features................................................................................................................ 441 10.1.2 Block Diagram ..................................................................................................... 445 10.1.3 Pin Configuration................................................................................................. 446 10.1.4 Register ...
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Usage Notes ...................................................................................................................... 521 Section 11 Programmable Pulse Generator (PPG) ............................................531 11.1 Overview........................................................................................................................... 531 11.1.1 Features................................................................................................................ 531 11.1.2 Block Diagram ..................................................................................................... 532 11.1.3 Pin Configuration................................................................................................. 533 11.1.4 Registers............................................................................................................... 534 11.2 Register Descriptions ........................................................................................................ 535 11.2.1 Next Data Enable Registers ...
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Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 563 12.2.6 Module Stop Control Register (MSTPCR) .......................................................... 566 12.3 Operation........................................................................................................................... 567 12.3.1 TCNT Incrementation Timing ............................................................................. 567 12.3.2 Compare Match Timing ....................................................................................... 568 12.3.3 Timing of TCNT External Reset.......................................................................... 570 ...
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Switching between Watchdog Timer Mode and Interval Timer Mode................ 595 13.5.4 System Reset by WDTOVF Signal...................................................................... 595 13.5.5 Internal Reset in Watchdog Timer Mode............................................................. 596 Section 14 Serial Communication Interface (SCI) ............................................597 14.1 Overview........................................................................................................................... 597 14.1.1 Features................................................................................................................ 597 14.1.2 ...
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Operation........................................................................................................................... 678 15.3.1 Overview.............................................................................................................. 678 15.3.2 Pin Connections ................................................................................................... 678 15.3.3 Data Format ......................................................................................................... 680 15.3.4 Register Settings .................................................................................................. 682 15.3.5 Clock.................................................................................................................... 684 15.3.6 Data Transfer Operations ..................................................................................... 686 15.3.7 Operation in GSM Mode ..................................................................................... 694 15.3.8 Operation in ...
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Module Stop Control Register (MSTPCR) .......................................................... 728 17.3 Operation........................................................................................................................... 728 Section 18 RAM ................................................................................................731 18.1 Overview........................................................................................................................... 731 18.1.1 Block Diagram ..................................................................................................... 731 18.1.2 Register Configuration......................................................................................... 732 18.2 Register Descriptions ........................................................................................................ 732 18.2.1 System Control Register (SYSCR) ...................................................................... 732 18.3 ...
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Programming/Erasing Flash Memory ............................................................................... 765 19.7.1 Program Mode ..................................................................................................... 765 19.7.2 Program-Verify Mode.......................................................................................... 766 19.7.3 Erase Mode .......................................................................................................... 768 19.7.4 Erase-Verify Mode............................................................................................... 768 19.8 Flash Memory Protection.................................................................................................. 770 19.8.1 Hardware Protection ............................................................................................ 770 19.8.2 Software Protection.............................................................................................. 770 19.8.3 Error ...
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System Control Register 2 (SYSCR2) ................................................................. 806 19.14.6 RAM Emulation Register (RAMER)................................................................... 807 19.15 On-Board Programming Modes........................................................................................ 809 19.15.1 Boot Mode ........................................................................................................... 809 19.15.2 User Program Mode............................................................................................. 815 19.16 Programming/Erasing Flash Memory ............................................................................... 817 19.16.1 Program Mode ..................................................................................................... 817 ...
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Register Descriptions ........................................................................................................ 859 19.23.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 859 19.23.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 862 19.23.3 Erase Block Register 1 (EBR1) ........................................................................... 865 19.23.4 Erase Block Registers 2 (EBR2) .......................................................................... 866 19.23.5 System Control ...
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Section 20 Clock Pulse Generator .....................................................................911 20.1 Overview........................................................................................................................... 911 20.1.1 Block Diagram ..................................................................................................... 911 20.1.2 Register Configuration......................................................................................... 912 20.2 Register Descriptions ........................................................................................................ 912 20.2.1 System Clock Control Register (SCKCR) ........................................................... 912 20.3 Oscillator........................................................................................................................... 914 20.3.1 Connecting a Crystal Resonator........................................................................... 914 ...
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DC Characteristics ............................................................................................... 936 22.1.3 AC Characteristics ............................................................................................... 940 22.1.4 A/D Conversion Characteristics........................................................................... 964 22.1.5 D/A Conversion Characteristics........................................................................... 965 22.2 Electrical Characteristics of F-ZTAT (H8S/2329B F-ZTAT, H8S/2329E F-ZTAT, H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) ....................................................................... 966 22.2.1 Absolute Maximum Ratings ................................................................................ ...
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C.13 Port G................................................................................................................................ 1255 Appendix D Pin States.......................................................................................1259 D.1 Port States in Each Mode .................................................................................................. 1259 Appendix E Product Lineup ..............................................................................1266 Appendix F Package Dimensions......................................................................1267 Rev.6.00 Sep. 27, 2007 Page xxx of xxx REJ09B0220-0600 ...
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Overview The H8S/2329 Group and H8S/2328 Group are series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas’ proprietary architecture, and equipped with supporting functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided ...
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Section 1 Overview Table 1.1 Overview Item Specification • CPU General-register machine ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control ⎯ Maximum clock rate: 25 MHz ...
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Item Specification • Data transfer Can be activated by internal interrupt or software controller (DTC) • Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc. • Request ...
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Section 1 Overview Item Specification • Memory Flash memory, mask ROM • High-speed static RAM Product Code H8S/2329B, H8S/2329E * H8S/2328 * H8S/2327 H8S/2326 H8S/2324S H8S/2323 H8S/2322R H8S/2321 H8S/2320 Notes: 1. The on-chip debug function can be used with the ...
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Item Specification • Operating modes Eight MCU operating modes (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) CPU Operating Mode Mode 1 — Advanced — Advanced Boot mode 11 12 — Advanced User ...
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Section 1 Overview Item Specification • Operating modes Four MCU operating modes (ROMless, mask ROM versions, H8S/2329B F-ZTAT) CPU Operating Mode Mode 1 — Advanced On-chip ROM disabled ...
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Item Specification Product lineup Operating power supply voltage Operating frequency Model O: Products in the current lineup Note: * The on-chip debug function can be used with the E10A emulator (E10A compatible version). However, some function modules and pin functions ...
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Section 1 Overview 1.2 Block Diagram EXTAL XTAL STBY RES WDTOVF (FWE, EMLE NMI PF /φ / /RD 5 Port PF /HWR /LWR 3 PF ...
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EXTAL XTAL STBY RES WDTOVF NMI Interrupt controller / φ / /RD 5 Port PF /HWR /LWR 3 PF /WAIT/BREQO 2 PF /BACK 1 PF /BREQ ...
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Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangement P5 /SCK /IRQ /ADTRG/IRQ /WAIT/BREQO ref /AN ...
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AV 103 CC V 104 ref P4 /AN 105 /AN 106 /AN 107 /AN 108 /AN 109 /AN 110 /AN /DA 111 ...
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Section 1 Overview / IRQ P5 /SCK /ADTRG/IRQ /WAIT/BREQO ref P4 / ...
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AV 103 CC V 104 ref 105 106 107 108 109 110 ...
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Section 1 Overview P5 /SCK /IRQ /ADTRG/IRQ /WAIT/BREQO ref /AN 98 ...
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AV 103 CC V 104 ref P4 /AN 105 /AN 106 /AN 107 /AN 108 /AN 109 /AN 110 /AN /DA 111 ...
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Section 1 Overview E10A compatible version / IRQ P5 /SCK /ADTRG/IRQ /WAIT/BREQO ref ...
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E10A compatible version AV 103 CC V 104 ref P4 /AN 105 /AN 106 /AN 107 /AN 108 /AN 109 /AN 110 ...
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Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode Pin No. TFP-120 FP-128B Mode ...
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Pin No. TFP-120 FP-128B Mode /IRQ /IRQ 6 — — /IRQ /IRQ 4 33 ...
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Section 1 Overview Pin No. TFP-120 FP-128B Mode /RxD /SCK /SCK /DREQ — — ...
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Pin No. TFP-120 FP-128B Mode XTAL 78 86 EXTAL /φ / HWR 84 92 ...
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Section 1 Overview Pin No. TFP-120 FP-128B Mode 4 101 111 P4 /AN 6 102 112 P4 /AN 7 103 113 AV SS 104 114 V SS 105 115 P1 /PO 7 TIOCB TCLKD 106 116 P1 /PO 6 TIOCA ...
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Pin No. TFP-120 FP-128B Mode 4 — — Notes: 1. Only modes 4 and 5 are provided in the ROMless version. 2. The DREQ0, TEND0, DREQ1, and TEND1 pin functions are not supported ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 Pin Functions Type Symbol Power Clock XTAL EXTAL φ Rev.6.00 Sep. 27, 2007 Page 24 of 1268 REJ09B0220-0600 Pin No. TFP-120 FP-128B I/O 1, 33, 5, 39, Input ...
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Type Symbol Operating mode control MD 0 Pin No. TFP-120 FP-128B I/O 115 to 125 to Input 113 123 Rev.6.00 Sep. 27, 2007 Page 25 of 1268 Section 1 Overview Name and Function Mode pins: These pins ...
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Section 1 Overview Type Symbol Operating mode control MD 0 RES System control STBY BREQ BREQO BACK Rev.6.00 Sep. 27, 2007 Page 26 of 1268 REJ09B0220-0600 Pin No. TFP-120 FP-128B I/O 115 to 125 to Input 113 ...
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Type Symbol 1 FWE * System control 2 EMLE * Interrupts NMI IRQ to 7 IRQ 0 Address bus Data bus Bus control ...
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Section 1 Overview Type Symbol CAS * 4 Bus control LCAS * 4 WAIT DREQ DMA controller , 1 DREQ 3 (DMAC TEND , 1 TEND 0 DACK , 1 DACK 0 16-bit timer TCLKD to pulse unit ...
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Type Symbol 16-bit timer TIOCA , 4 pulse unit TIOCB 4 (TPU) TIOCA , 5 TIOCB 5 Programmable pulse generator PO 0 (PPG) 8-bit timer TMO , 0 TMO 1 TMCI , 0 TMCI 1 TMRI , ...
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Section 1 Overview Type Symbol A/D converter AV CC and D/A converter ref I/O ports ...
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Type Symbol I/O ports ...
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Section 1 Overview Rev.6.00 Sep. 27, 2007 Page 32 of 1268 REJ09B0220-0600 ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate: ⎯ 8/16/32-bit register-register add/subtract ⎯ 8 × 8-bit register-register multiply: ⎯ 16 ÷ 8-bit register-register divide: ⎯ 16 ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2329 and H8S/2328 Group CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception ...
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Address Space Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'00000000 H'00FFFFFF H'FFFFFFFF Program area Cannot be used by the ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than ...
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Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register ...
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General Register Data Formats Figure 2.7 shows the data formats in general registers. Data Type Register Number 1-bit data RnH 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Byte data RnL Figure 2.7 ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP * , PUSH * ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Function Instruction MOV BWL BWL Data transfer POP, PUSH — — ...
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Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source ...
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Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM 1 Size * Function (EAs) → Rd, Rs → (Ead) B/W/L Moves data between two general registers or between a general register and ...
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Section 2 CPU Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Rev.6.00 Sep. 27, 2007 Page 52 of 1268 REJ09B0220-0600 1 Size * Function Rd ± Rs → Rd, Rd ± ...
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Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS 1 Size * Function Rd ÷ Rs → Rd B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit ...
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Section 2 CPU Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Rev.6.00 Sep. 27, 2007 Page 54 of 1268 REJ09B0220-0600 1 Size * Function Rd ∧ Rs → Rd, Rd ...
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Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR 1 Size * Function 1 → (<bit-No.> of <EAd>) B Sets a specified bit in a general register or memory operand to 1. The bit number is ...
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Section 2 CPU Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Rev.6.00 Sep. 27, 2007 Page 56 of 1268 REJ09B0220-0600 1 Size * Function C ⊕ (<bit-No.> of <EAd>) → Exclusive-ORs the carry flag with ...
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Type Instruction Branch Bcc instructions JMP BSR JSR RTS 1 Size * Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ ...
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Section 2 CPU Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP Rev.6.00 Sep. 27, 2007 Page 58 of 1268 REJ09B0220-0600 1 Size * Function — Starts trap-instruction exception handling. — Returns from an exception-handling ...
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Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 1 Size ...
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Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...
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Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand ...
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Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
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Section 2 CPU If an odd address is specified in word or longword memory access branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at ...
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Table 2.6 Effective Address Calculation Section 2 CPU Rev.6.00 Sep. 27, 2007 Page 65 of 1268 REJ09B0220-0600 ...
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Section 2 CPU Rev.6.00 Sep. 27, 2007 Page 66 of 1268 REJ09B0220-0600 ...
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Section 2 CPU Rev.6.00 Sep. 27, 2007 Page 67 of 1268 REJ09B0220-0600 ...
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Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.11 shows a diagram of the processing states. Figure 2.12 ...
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End of bus request Bus-released state End of exception handling Exception-handling state RES = high *1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition ...
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Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the ...
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Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from ...
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Section 2 CPU Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Note: * Ignored when returning. Figure 2.13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions ...
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Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and ...
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Section 2 CPU φ Internal address bus Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Figure 2.14 On-Chip Memory Access Cycle φ Address bus AS RD HWR, LWR Data bus Figure 2.15 ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.16 shows the access ...
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Section 2 CPU φ Address bus AS RD HWR, LWR Data bus Figure 2.17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) The H8S/2328B F-ZTAT and H8S/2326 F-ZTAT have eight operating modes (modes 10, 11, 14 and 15). These modes are determined by the ...
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Section 3 MCU Operating Modes The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT actually accesses a maximum of 16 Mbytes. Modes are externally expanded modes that allow access ...
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Table 3.2 MCU Operating Mode Selection (Mask ROM and ROMless Versions, H8S/2329B F-ZTAT) MCU Operating Mode ...
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Section 3 MCU Operating Modes 3.1.3 Register Configuration The H8S/2329 Group and H8S/2328 Group have a mode control register (MDCR) that indicates the inputs at the mode pins (MD control register 2 (SYSCR2) * registers. Table 3.3 Registers Name Mode ...
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System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit is always read as 0, and cannot be modified. Bits ...
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Section 3 MCU Operating Modes Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ IRQ to IRQ input is always performed from one of the ports Bit 1 IRQPAS Description are used for IRQ ...
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Bit 3 FLSHE Description 0 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB 1 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 and 1—Reserved: These bits are always read as 0. Only ...
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Section 3 MCU Operating Modes 3.3.5 Mode 5 (Expanded Mode with On-Chip ROM Disabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, ...
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Mode 11 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is ...
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Section 3 MCU Operating Modes Table 3.4 Pin Functions in Each Mode Mode Mode Port Port ...
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Mode 2 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'060000 Reseved area H'080000 External address H'FF7400 Reseved area H'FF7C00 On-chip RAM External address H'FFFC00 H'FFFE50 H'FFFF08 External address H'FFFF28 H'FFFFFF ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'060000 *4 Reseved area H'080000 External address space H'FF7400 *4 Reseved area H'FF7C00 *3 On-chip RAM External address H'FFFC00 space ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *3 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External addresses ...
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Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 H'010000 external address H'040000 External address H'FFDC00 External address H'FFFC00 H'FFFE50 H'FFFF08 External address H'FFFF28 H'FFFFFF Notes: 1. External addresses when EAE = ...
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Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address space H'040000 External address space H'FFDC00 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *4 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *3 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External addresses ...
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Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 H'010000 external address H'080000 External address H'FFDC00 External address H'FFFC00 H'FFFE50 H'FFFF08 External address H'FFFF28 H'FFFFFF Notes: 1. External addresses when EAE = ...
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Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address space H'080000 External address space H'FFDC00 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space ...
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Section 3 MCU Operating Modes Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.5 H8S/2324S Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 96 of 1268 REJ09B0220-0600 Modes ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *2 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External addresses ...
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Section 3 MCU Operating Modes Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.7 H8S/2322R Memory Map in Each Operating Mode Rev.6.00 Sep. 27, 2007 Page 98 of 1268 REJ09B0220-0600 Modes ...
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Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.8 H8S/2320 and H8S/2321 Memory Map in Each Operating Mode Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External ...
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Section 3 MCU Operating Modes Rev.6.00 Sep. 27, 2007 Page 100 of 1268 REJ09B0220-0600 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extend register (EXR) are pushed onto the stack. 2. ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 2 ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU ...
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RES Address bus RD HWR, LWR (1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2), (4) Start address (contents of reset exception vector address) (5) Start address ((5) = ...
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Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources and the number of interrupts of each type. The ...
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Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address ...
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Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the ...
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Section 4 Exception Handling Rev.6.00 Sep. 27, 2007 Page 110 of 1268 REJ09B0220-0600 ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features. This chapter assumes the maximum number of interrupt sources available in these series—nine external interrupts ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request SWDTEND to TEI ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests 5.1.4 Register Configuration Table 5.2 summarizes the registers ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for ...
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Interrupt Priority Registers (IPRA to IPRK) Bit : 7 — Initial value : 0 R/W : — The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels for interrupts other than ...
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Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 R/W : R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB ...
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Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : 7 IRQ7F IRQ6F Initial value : 0 R/(W) * R/(W) * R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to ...
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Section 5 Interrupt Controller IRQnSCA, IRQnSCB Edge/level detection circuit IRQn input Note Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF The ...
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Internal Interrupts There are 52 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. ...
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Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Source Source Power-on reset Reserved Reserved for system use Trace Reserved for system use NMI External pin Trap instruction (4 sources) Reserved for ...
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Origin of Interrupt Interrupt Source Source SWDTEND (software- DTC activated data transfer end) WOVI (interval timer) Watchdog timer 3 CMI (compare match) * Refresh controller Reserved — ADI (A/D conversion A/D end) Reserved — TGI0A (TGR0A input TPU capture/compare channel ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source TGI1A (TGR1A input TPU capture/compare channel 1 match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input TPU capture/compare channel 2 match) TGI2B (TGR2B input ...
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Origin of Interrupt Interrupt Source Source TGI4A (TGR4A input TPU capture/compare channel 4 match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input TPU capture/compare channel 5 match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source DEND0A (channel DMAC 0/channel 0A transfer 3 end) * DEND0B (channel 0B 3 transfer end) * DEND1A (channel 1/channel 1A transfer 3 end) * DEND1B (channel 1B 3 transfer end) ...
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Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In ...
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Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I ...
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Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, ...
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Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit ...
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Program execution state Interrupt generated? Yes No IRQ0? Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Section 5 Interrupt Controller No ...
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Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. ...
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Program execution state Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt ...
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Section 5 Interrupt Controller 5.4.4 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...
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Figure 5.7 Interrupt Exception Handling Rev.6.00 Sep. 27, 2007 Page 135 of 1268 Section 5 Interrupt Controller REJ09B0220-0600 ...
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Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table ...
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Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is ...
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Section 5 Interrupt Controller 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When ...
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DTC and DMAC Activation by Interrupt 5.6.1 Overview The DTC and DMAC * can be activated by an interrupt. In this case, the following options are available. 1. Interrupt request to CPU 2. Activation request to DTC 3. Activation ...
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Section 5 Interrupt Controller 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC, DMAC * , and interrupt controller. Note: * The DMAC is not supported in the H8S/2321. Interrupt request IRQ interrupt Interrupt source On-chip clear ...
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Operation The interrupt controller has three main functions in DTC and DMAC * control. Selection of Interrupt Source: With the DMAC * , the activation source is input directly to each channel. The activation source for each DMAC * ...
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Section 5 Interrupt Controller Table 5.11 Interrupt Source Selection and Clearing Control Settings DMAC DTA DTCE Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag ...
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Section 6 Bus Controller 6.1 Overview The chip has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently ...
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Section 6 Bus Controller • Idle cycle insertion ⎯ An idle cycle can be inserted in case of an external read cycle between different areas ⎯ An idle cycle can be inserted when an external read cycle is immediately followed ...
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Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 External bus control signals BREQ BACK BREQO WAIT External DRAM signals* Note: * Not supported in the H8S/2321. Figure 6.1 Block Diagram of Bus ...
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Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Address strobe Read High write/write enable Low write Chip select 0 Chip select 1 Chip select 2/row address ...
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Name Chip select 6 Chip select 7 Upper column address strobe Lower column strobe Wait Bus request Bus request acknowledge Bus request output Note: * The DRAM interface and the CAS and LCAS pin functions are not supported in the ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus control ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 ABW6 Modes Initial value : 1 R/W : R/W Mode 4 Initial value : 0 R/W : R/W ABWCR is an 8-bit readable/writable register ...
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Section 6 Bus Controller 6.2.2 Access State Control Register (ASTCR) Bit : 7 AST7 AST6 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal ...
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Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is ...
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Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is ...
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Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description 0 Idle cycle not inserted ...
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Section 6 Bus Controller Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 ...
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Bus Control Register L (BCRL) Bit : 7 BRLE BREQOE Initial value : 0 R/W : R/W Note: * This bit is reserved in the H8S/2321. BCRL is an 8-bit readable/writable register that performs selection of the external bus-released ...
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Section 6 Bus Controller Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF * to be internal addresses or external addresses. H8S/2329B, H8S/2328 * Bit 5 H8S/2326 0 On-chip ROM Addresses H'010000 to H'03FFFF * ...
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Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle or DMAC single address cycle. In the H8S/2321 this bit is reserved and should only be written with 0. ...
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Section 6 Bus Controller Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (T used when areas designated as DRAM space are accessed. Bit 7 TPC Description 0 1-state precharge cycle is inserted ...
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Bit 3 Bit 2 MXC1 MXC0 Description 0 0 8-bit shift • When 8-bit access space is designated: Row address A for comparison • When 16-bit access space is designated: Row address A for comparison 1 9-bit shift • When ...
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Section 6 Bus Controller 6.2.7 DRAM Control Register (DRAMCR) Bit : 7 RFSHE RCW Initial value : 0 R/W : R/W DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the ...
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Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR. Bit 4 ...
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Section 6 Bus Controller 6.2.8 Refresh Timer Counter (RTCNT) Bit : 7 Initial value : 0 R/W : R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. ...
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Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas 2-Mbyte units, and performs bus control for external space in area units. Figure 6.2 ...
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Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and ...
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Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL ABWCR ASTCR ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The chip’s memory interfaces comprise a basic bus ...
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Section 6 Bus Controller 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, ...