D12321VF20V Renesas Electronics America, D12321VF20V Datasheet - Page 15

• Manufacturer Part Number: D12321VF20V
• Description: IC H8S/2321 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4.2
4.3
4.4
4.5
4.6
4.7
Section 5 Interrupt Controller ............................................................................111
5.1
5.2
5.3
5.4
5.5
4.1.2
4.1.3
Reset.................................................................................................................................. 104
4.2.1
4.2.2
4.2.3
4.2.4
Traces................................................................................................................................ 106
Interrupts ........................................................................................................................... 107
Trap Instruction................................................................................................................. 108
Stack Status after Exception Handling.............................................................................. 108
Notes on Use of the Stack ................................................................................................. 109
Overview........................................................................................................................... 111
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 114
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources ............................................................................................................... 119
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 127
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Usage Notes ...................................................................................................................... 137
5.5.1
5.5.2
5.5.3
5.5.4
Exception Handling Operation............................................................................. 102
Exception Vector Table ....................................................................................... 102
Overview.............................................................................................................. 104
Reset Sequence .................................................................................................... 104
Interrupts after Reset............................................................................................ 105
State of On-Chip Supporting Modules after Reset Release ................................. 105
Features................................................................................................................ 111
Block Diagram ..................................................................................................... 112
Pin Configuration................................................................................................. 113
Register Configuration......................................................................................... 113
System Control Register (SYSCR) ...................................................................... 114
Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 115
IRQ Enable Register (IER) .................................................................................. 116
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 117
IRQ Status Register (ISR).................................................................................... 118
External Interrupts ............................................................................................... 119
Internal Interrupts................................................................................................. 121
Interrupt Exception Vector Table ........................................................................ 121
Interrupt Control Modes and Interrupt Operation ................................................ 127
Interrupt Control Mode 0 ..................................................................................... 130
Interrupt Control Mode 2 ..................................................................................... 132
Interrupt Exception Handling Sequence .............................................................. 134
Interrupt Response Times .................................................................................... 136
Contention between Interrupt Generation and Disabling..................................... 137
Instructions that Disable Interrupts ...................................................................... 138
Times when Interrupts Are Disabled ................................................................... 138
Interrupts during Execution of EEPMOV Instruction.......................................... 138
Rev.6.00 Sep. 27, 2007 Page xiii of xxx
REJ09B0220-0600